A42L8316 Series
Selection Guide
Symbol
Description
-30
-35
-40
Unit
tRAC
30
35
40
ns
Maximum RAS Access Time
tAA
Maximum Column Address Access Time
Maximum CAS Access Time
16
9
17
10
18
11
ns
ns
tCAC
tOEA
9
10
11
ns
Maximum Output Enable ( OE) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
tRC
tPC
54
14
62
16
70
18
ns
ns
Functional Description
The A42L8316 reads and writes data by multiplexing an
18-bit address into a 9-bit row and 9-bit column address.
The A42L8316 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
and
are used to strobe the row address and the
keeps the output drivers on during the
precharge
RAS
CAS
CAS
column address, respectively.
time (tcp). Since data can be output after
goes high,
CAS
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
The A42L8316 has two
CAS
inputs:
controls I/O0-
LCAS
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
I/O7, and
controls I/O8 - I/O15,
and
UCAS
UCAS
LCAS
function in an identical manner to
in that either will
CAS
generate an internal
signal. The
function and
CAS
CAS
CAS
timing are determined by the first
(
or
UCAS
A memory cycle is terminated by returning both RAS and
) to transition low and by the last to transition high.
LCAS
high. Memory cell data will retain its correct state by
maintaining power and accessing all 512 combinations of
the 9-bit row addresses, regardless of sequence, at least
CAS
Byte Read and Byte Write are controlled by using
LCAS
and
separately.
UCAS
once every 8ms through any RAS cycle (Read, Write) or
A Read cycle is performed by holding the WE signal high
during RAS/ operation. A Write cycle is executed by
RAS Refresh cycle (RAS-only, CBR, or Hidden). The CBR
Refresh cycle automatically controls the row addresses by
invoking the refresh counter and controller.
CAS
holding the WE signal low during RAS /
operation;
CAS
the input data is latched by the falling edge of WE or
, whichever occurs later. The data inputs and outputs
Power-On
CAS
are routed through 16 common I/O pins, with RAS,
,
CAS
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
WE and OE controlling the in direction.
containing a RAS clock. During Power-On, the VCC
EDO Page Mode operation all 512 columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
current is dependent on the input levels of RAS and
.
CAS
It is recommended that RAS and
track with VCC or
CAS
be held at a valid VIH during Power-On to avoid current
surges.
latched by RAS followed by a column address latched by
. While holding RAS low,
can be toggled to
CAS
CAS
strobe changing column addresses, thus achieving shorter
cycle times.
PRELIMINARY
(August, 2002, Version 0.1)
2
AMIC Technology, Inc.
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