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A2F060M3E-FGG256I

更新时间： 2024-01-26 00:24:14

品牌	Logo	应用领域
美高森美 - MICROSEMI		现场可编程门阵列可编程逻辑
页数	文件大小	规格书
192页	11779K
描述
SmartFusion Customizable System-on-Chip (cSoC)

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A2F060M3E-FGG256I 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LBGA, BGA256,16X16,40	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.82
最大时钟频率：	80 MHz	JESD-30 代码：	S-PBGA-B256
JESD-609代码：	e1	长度：	17 mm
湿度敏感等级：	3	可配置逻辑块数量：	1536
等效关口数量：	60000	输入次数：	66
逻辑单元数量：	1536	输出次数：	66
端子数量：	256	组织：	1536 CLBS, 60000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA256,16X16,40	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	250
电源：	1.5,1.8,2.5,3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	1.7 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	17 mm
Base Number Matches：	1

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SmartFusion Customizable System-on-Chip (cSoC)

devices from the PCB design. Flash-based SmartFusion cSoCs simplify total system design and reduce

cost and design risk, while increasing system reliability.

Immunity to Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the atmosphere, strike a

configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O configuration behavior in an unpredictable

way.

Another source of radiation-induced firm errors is alpha particles. For alpha radiation to cause a soft or

firm error, its source must be in very close proximity to the affected circuit. The alpha source must be in

the package molding compound or in the die itself. While low-alpha molding compounds are being used

increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.

Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not occur in SmartFusion cSoCs. Once it is programmed, the

flash cell configuration element of SmartFusion cSoCs cannot be altered by high energy neutrons and is

therefore immune to errors from them. Recoverable (or soft) errors occur in the user data SRAMs of all

FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry

built into the FPGA fabric.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

The I/Os are controlled by the JTAG Boundary Scan register during programming, except for the analog

pins (AC, AT and AV). The Boundary Scan register of the AG pin can be used to enable/disable the gate

driver in software v9.0.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-1 on page 1-4).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

Revision 10

1-3

1...8 9 101112 13 14...192

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与A2F060M3E-FGG256I相关器件

型号	品牌	描述	获取价格	数据表
A2F060M3E-FGG256Y	MICROSEMI	SmartFusion Customizable System-on-Chip (cSoC)	获取价格
A2F060M3E-FGG256Y	ACTEL	Field Programmable Gate Array, 1536 CLBs, 60000 Gates, CMOS, PBGA256, 1 MM PITCH, GREEN, F	获取价格
A2F060M3E-FGG256YC	MICROSEMI	FPGA	获取价格
A2F060M3E-FGG256YES	MICROSEMI	SmartFusion Customizable System-on-Chip (cSoC)	获取价格
A2F060M3E-FGG256YI	MICROSEMI	SmartFusion Customizable System-on-Chip (cSoC)	获取价格
A2F060M3E-FGG256YI	ACTEL	Field Programmable Gate Array, 1536 CLBs, 60000 Gates, CMOS, PBGA256, 1 MM PITCH, GREEN, F	获取价格

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