Datasheet > A2F060M3D-1FG256YM

A2F060M3D-1FG256YM

更新时间： 2024-11-27 15:42:31

品牌	Logo	应用领域
美高森美 - MICROSEMI		栅可编程逻辑
页数	文件大小	规格书
154页	9578K
描述
Field Programmable Gate Array,

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技术参数
数据手册

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A2F060M3D-1FG256YM 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.83	JESD-609代码：	e0
湿度敏感等级：	3	峰值回流温度（摄氏度）：	225
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	端子面层：	TIN LEAD
处于峰值回流温度下的最长时间：	20	Base Number Matches：	1

A2F060M3D-1FG256YM 数据手册

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Revision 2

Military Grade SmartFusion Customizable System-on-Chip (cSoC)

•

Embedded SRAMs and FIFOs

Product Benefits

–

Variable Aspect Ratio 4,608-Bit SRAM Blocks

x1, x2, x4, x9, and x18 Organizations

True Dual-Port SRAM (excluding x18)

•

100% Military Temperature Tested and Qualified from

–55°C to 125°C

•

Not Susceptible to Neutron-Induced Configuration Loss

Programmable Embedded FIFO Control Logic

Microcontroller Subsystem (MSS)

•

Secure ISP with 128-Bit AES via JTAG

FlashLock^®to Secure FPGA Contents

Five Clock Conditioning Circuits (CCCs) with up to 2

Integrated Analog PLLs

•

Hard 50 MHz 32-Bit ARM^®Cortex^®-M3

–

Fully Tested Across Military Temperature Range

(–55°C to 125°C)

–

1.25 DMIPS/MHz Throughput from Zero Wait State

Memory

Memory Protection Unit (MPU)

Single Cycle Multiplication, Hardware Divide

JTAG Debug (4 wires), Serial Wire Debug (SWD, 2

wires), and Single Wire Viewer (SWV) Interfaces

–

Phase Shift, Multiply/Divide, and Delay Capabilities

Frequency: Input 1.5–350 MHz, Output 0.75 to

350 MHz

–

Programmable Analog

Analog Front-End (AFE)

•

Up to Three 12-Bit SAR ADCs

•

Internal Memory

–

500 Ksps in 12-Bit Mode

550 Ksps in 10-Bit Mode

600 Ksps in 8-Bit Mode

Embedded Nonvolatile Flash Memory (eNVM), 128

Kbytes to 512 Kbytes

Embedded High-Speed SRAM (eSRAM), 16 Kbytes

to 64 Kbytes, Implemented in 2 Physical Blocks to

–

•

Internal 2.56

Reference

Reference or Optional External

Enable Simultaneous Access from

Masters

2 Different

One First-Order  DAC (sigma-delta) per ADC

12-Bit 500 Ksps Update Rate

–

Multi-Layer AHB Communications Matrix

–

Up to 5 High-Performance Analog Signal Conditioning

Blocks (SCB) per Device, Each Including:

–

Provides up to 16 Gbps of On-Chip Memory

Bandwidth,¹Allowing Multi-Master Schemes

Two High-Voltage Bipolar Voltage Monitors (with 4

input ranges from ±2.5 V to –11.5/12 V) with 4%

Accuracy

High Gain Current Monitor, Differential Gain = 50, up

to 12 V Common Mode

•

10/100 Ethernet MAC with RMII Interface²

Programmable External Memory Controller, Which

Supports:

–

Asynchronous Memories

NOR Flash, SRAM, PSRAM

Synchronous SRAMs

Temperature Monitor (Resolution = ¼°C in 12-Bit

Mode; Accurate from –55°C to 150°C)

•

Two I²C Peripherals

•

Up to Ten High-Speed Voltage Comparators

(t_pd= 15 ns)

Two 16550 Compatible UARTs

Two SPI Peripherals

Analog Compute Engine (ACE)

Two 32-Bit Timers

32-Bit Watchdog Timer

8-Channel DMA Controller to Offload the Cortex-M3

processor from Data Transactions

Clock Sources

•

Offloads Cortex-M3–Based MSS from Analog

Initialization and Processing of ADC, DAC, and SCBs

Sample Sequence Engine for ADC and DAC Parameter

Set-Up

•

Post-Processing Engine for Functions such as Low-

Pass Filtering and Linear Transformation

Easily Configured via GUI in Libero^®System-on-Chip

(SoC) Software

–

32 kHz to 20 MHz Main Oscillator

Battery-Backed 32 KHz Low Power Oscillator with

Real-Time Counter (RTC)

–

100 MHz Embedded RC Oscillator; Up to 3%

Accurate at Military Temperature

Embedded Analog PLL with 4 Output Phases (0, 90,

180, 270)

I/Os and Operating Voltage

•

FPGA I/Os

–

LVDS, PCI, PCI-X, up to 24 mA IOH/IOL

Up to 350 MHz

High-Performance FPGA

•

Based on proven ProASIC^®3 FPGA Fabric

Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,

Flash-Based CMOS Process

•

MSS I/Os

–

Schmitt Trigger, up to 6 mA IOH, 8 mA IOL

Up to 180 MHz

•

Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

External 1.5 V Is Allowed by Bypassing Regulator

(digital VCC = 1.5 V for FPGA and MSS, analog VCC =

3.3 V and 1.5 V)

•

Nonvolatile, Live at Power-Up, Retains Program When

Powered Off

350 MHz System Performance

1 Theoretical maximum

2 A2F500 devices

March 2015

12 3 4 5 6 7...154

中文翻译

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与A2F060M3D-1FG256YM相关器件

型号	品牌	获取价格	描述	数据表
A2F060M3D-1FG288	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG288ES	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG288I	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG288Y	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG288YES	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG288YI	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG484	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG484ES	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG484I	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)
A2F060M3D-1FG484Y	MICROSEMI	获取价格	SmartFusion Customizable System-on-Chip (cSoC)

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