Datasheet > A29800TM-90I

A29800TM-90I

更新时间： 2024-02-17 17:51:36

品牌	Logo	应用领域
联笙电子 - AMICC		光电二极管
页数	文件大小	规格书
37页	412K
描述
Flash, 512KX16, 90ns, PDSO44

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A29800TM-90I 数据手册

A29800 Series

Word/Byte Configuration

Program and Erase Operation Status

During an erase or program operation, the system may check

the status of the operation by reading the status bits on I/O⁷-

I/O⁰. Standard read cycle timings and ICC read specifications

apply. Refer to "Write Operation Status" for more information,

and to each AC Characteristics section for timing diagrams.

The

pin determines whether the I/O pins I/O15 - I/O0

BYTE

operate in the byte or word configuration. If the

pin is

BYTE

set at logic “1”, the device is in word configuration, I/O¹⁵- I/O0

are active and controlled by and

If the

pin is set at logic “0”, the device is in byte

BYTE

configuration, and only I/O⁰- I/O7 are active and controlled by

and . I/O8- I/O14 are tri-stated, and I/O15 pin is used as

Standby Mode

When the system is not reading or writing to the device, it can

place the device in the standby mode. In this mode, current

consumption is greatly reduced, and the outputs are placed in

an input for the LSB(A-1) address function.

Requirements for Reading Array Data

the high impedance state, independent of the

input.

To read array data from the outputs, the system must drive

The device enters the CMOS standby mode when the

the

and

pins to VIL.

is the power control and

pins are both held at VCC ± 0.5V. (Note that this is a

RESET

more restricted voltage range than VIH.) The device enters the

TTL standby mode when is held at VIH, while is

selects the device.

data to the output pins.

is the output control and gates array

RESET

should remain at VIH all the time

held at VCC±0.5V. The device requires the standard access

time (tCE) before it is ready to read data.

during read operation. The internal state machine is set for

reading array data upon device power-up, or after a hardware

reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid addresses on the

device address inputs produce valid data on the device data

outputs. The device remains enabled for read access until the

command register contents are altered.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

ICC3 in the DC Characteristics tables represents the standby

current specification.

Output Disable Mode

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to the

Read Operations Timings diagram for the timing waveforms,

l^CC1in the DC Characteristics table represents the active

current specification for reading array data.

When the

input is at VIH, output from the device is

disabled. The output pins are placed in the high impedance

state.

: Hardware Reset Pin

RESET

Writing Commands/Command Sequences

The

pin provides a hardware method of resetting the

RESET

device to reading array data. When the system drives the

pin low for at least a period of tRP, the device

To write a command or command sequence (which includes

programming data to the device and erasing sectors of

RESET

memory), the system must drive

and

to VIL, and

immediately terminates any operation in progress, tristates all

data output pins, and ignores all read/write attempts for the

to VIH. An erase operation can erase one sector, multiple

duration of the

pulse. The device also resets the

RESET

sectors, or the entire device. The Sector Address Tables

indicate the address range that each sector occupies. A

"sector address" consists of the address inputs required to

uniquely select a sector. See the "Command Definitions"

section for details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

internal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data

integrity.

The

pin may be tied to the system reset circuitry. A

RESET

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then

read autoselect codes from the internal register (which is

separate from the memory array) on I/O⁷- I/O0. Standard read

cycle timings apply in this mode. Refer to the "Autoselect

Mode" and "Autoselect Command Sequence" sections for

more information.

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

Refer to the AC Characteristics tables for

and diagram.

parameters

RESET

ICC2 in the DC Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

(December, 2009, Version 1.7)

AMIC Technology, Corp.

1...3 4 567 8 9...37

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与A29800TM-90I相关器件

型号	品牌	描述	获取价格	数据表
A29800TM-90IF	AMICC	Flash, 512KX16, 90ns, PDSO44, ROHS COMPLIANT, SOP-44	获取价格
A29800TV-55	AMICC	1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A29800TV-55F	AMICC	Flash, 512KX16, 55ns, PDSO48, ROHS COMPLIANT, TSOP1-48	获取价格
A29800TV-55I	AMICC	Flash, 512KX16, 55ns, PDSO48	获取价格
A29800TV-55IF	AMICC	Flash, 512KX16, 55ns, PDSO48, ROHS COMPLIANT, TSOP1-48	获取价格
A29800TV-70	AMICC	1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A29800TV-70F	AMICC	Flash, 512KX16, 70ns, PDSO48, ROHS COMPLIANT, TSOP1-48	获取价格
A29800TV-70I	AMICC	Flash, 512KX16, 70ns, PDSO48	获取价格
A29800TV-70IF	AMICC	Flash, 512KX16, 70ns, PDSO48, ROHS COMPLIANT, TSOP1-48	获取价格
A29800TV-90	AMICC	1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A29800TV-90F	AMICC	Flash, 512KX16, 90ns, PDSO48, ROHS COMPLIANT, TSOP1-48	获取价格
A29800TV-90I	AMICC	Flash, 512KX16, 90ns, PDSO48	获取价格
A29800TV-90IF	AMICC	Flash, 512KX16, 90ns, PDSO48, ROHS COMPLIANT, TSOP1-48	获取价格
A29800UM-55	AMICC	1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A29800UM-55F	AMICC	暂无描述	获取价格
A29800UM-55I	AMICC	Flash, 512KX16, 55ns, PDSO44	获取价格
A29800UM-55IF	AMICC	Flash, 512KX16, 55ns, PDSO44, ROHS COMPLIANT, SOP-44	获取价格
A29800UM-70	AMICC	1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A29800UM-70F	AMICC	Flash, 512KX16, 70ns, PDSO44, ROHS COMPLIANT, SOP-44	获取价格
A29800UM-70I	AMICC	Flash, 512KX16, 70ns, PDSO44	获取价格

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