5秒后页面跳转
A29040CL-55F PDF预览

A29040CL-55F

更新时间: 2024-01-12 13:12:20
品牌 Logo 应用领域
联笙电子 - AMICC 内存集成电路
页数 文件大小 规格书
28页 343K
描述
Flash, 512KX8, 55ns, PQCC32, ROHS COMPLIANT, PLASTIC, LCC-32

A29040CL-55F 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:unknown风险等级:5.49
最长访问时间:55 nsJESD-30 代码:R-PQCC-J32
长度:13.97 mm内存密度:4194304 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1端子数量:32
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
编程电压:5 V座面最大高度:3.4 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
类型:NOR TYPE宽度:11.43 mm
Base Number Matches:1

A29040CL-55F 数据手册

 浏览型号A29040CL-55F的Datasheet PDF文件第1页浏览型号A29040CL-55F的Datasheet PDF文件第3页浏览型号A29040CL-55F的Datasheet PDF文件第4页浏览型号A29040CL-55F的Datasheet PDF文件第5页浏览型号A29040CL-55F的Datasheet PDF文件第6页浏览型号A29040CL-55F的Datasheet PDF文件第7页 
A29040C Series  
512K X 8 Bit CMOS 5.0 Volt-only,  
Uniform Sector Flash Memory  
Preliminary  
Features  
- Embedded Program algorithm automatically writes and  
verifies bytes at specified addresses  
„ 5.0V ± 10% for read and write operations  
„ Access times:  
„ Minimum 100,000 program/erase cycles per sector  
„ 10-year data retention  
- 55/70 (max.)  
„ Current:  
- Reliable operation for the life of the system  
„ Compatible with JEDEC-standards  
- 20 mA typical active read current  
- 30 mA typical program/erase current  
- 1 μA typical CMOS standby  
- Pinout and software compatible with single-power-  
supply Flash memory standard  
- Superior inadvertent write protection  
„ Flexible sector architecture  
- 8 uniform sectors of 64 Kbyte each  
- Any combination of sectors can be erased  
- Supports full chip erase  
„
Polling and toggle bits  
Data  
- Provides a software method of detecting completion of  
program or erase operations  
„ Erase Suspend/Erase Resume  
- Sector protection:  
A hardware method of protecting sectors to prevent  
any inadvertent program or erase operations within that  
sector  
- Suspends a sector erase operation to read data from,  
or program data to, a non-erasing sector, then  
resumes the erase operation  
„ Extended operating temperature range: -40°C~+85°C  
for –U series  
„ Package options  
„ Embedded Erase Algorithms  
- Embedded Erase algorithm will automatically erase the  
entire chip or any combination of designated sectors  
and verify the erased sectors  
- 32-pin P-DIP, PLCC, or TSOP (Forward type)  
- All Pb-free (Lead-free) products are RoHS compliant  
General Description  
Reading data out of the device is similar to reading from  
other Flash or EPROM devices.  
The A29040C is a 5.0 volt-only Flash memory organized as  
524,288 bytes of 8 bits each. The 512 Kbytes of data are  
further divided into eight sectors of 64 Kbytes each for flexible  
sector erase capability. The 8 bits of data appear on I/O0 -  
I/O7 while the addresses are input on A0 to A18. The  
A29040C is offered in 32-pin PLCC, TSOP, and PDIP  
packages. This device is designed to be programmed in-  
system with the standard system 5.0volt VCC supply.  
Additional 12.0 volt VPP is not required for in-system write or  
erase operations. However, the A29040C can also be  
programmed in standard EPROM programmers.  
The A29040C has a second toggle bit, I/O2, to indicate  
whether the addressed sector is being selected for erase, and  
also offers the ability to program in the Erase Suspend mode.  
The standard A29040C offers access times of 55 and 70 ns,  
allowing high-speed microprocessors to operate without wait  
states. To eliminate bus contention the device has separate  
Device programming occurs by writing the proper program  
command sequence. This initiates the Embedded Program  
algorithm - an internal algorithm that automatically times the  
program pulse widths and verifies proper program margin.  
Device erasure occurs by executing the proper erase  
command sequence. This initiates the Embedded Erase  
algorithm  
-
an internal algorithm that automatically  
preprograms the array (if it is not already programmed)  
before executing the erase operation. During erase, the  
device automatically times the erase pulse widths and  
verifies proper erase margin.  
The host system can detect whether a program or erase  
operation is complete by reading the I/O7 (  
Polling) and  
Data  
I/O6 (toggle) status bits. After a program or erase cycle has  
been completed, the device is ready to read array data or  
accept another command.  
chip enable (  
), write enable (  
) and output enable  
WE  
CE  
The sector erase architecture allows memory sectors to be  
erased and reprogrammed without affecting the data  
contents of other sectors. The A29040C is fully erased when  
shipped from the factory.  
The hardware sector protection feature disables operations  
for both program and erase in any combination of the sectors  
of memory. This can be achieved via programming  
equipment.  
The Erase Suspend feature enables the user to put erase on  
hold for any period of time to read data from, or program  
data to, any other sector that is not selected for erasure.  
True background erase can thus be achieved.  
Power consumption is greatly reduced when the device is  
placed in the standby mode.  
(
) controls.  
OE  
The device requires only a single 5.0 volt power supply for  
both read and write functions. Internally generated and  
regulated voltages are provided for the program and erase  
operations.  
The A29040C is entirely software command set compatible  
with the JEDEC single-power-supply Flash standard.  
Commands are written to the command register using  
standard microprocessor write timings. Register contents  
serve as input to an internal state-machine that controls the  
erase and programming circuitry.  
Write cycles also internally latch addresses and data  
needed for the programming and erase operations.  
PRELIMINARY (May, 2013, Version 0.0)  
1
AMIC Technology, Corp.  

与A29040CL-55F相关器件

型号 品牌 描述 获取价格 数据表
A29040CL-55UF AMICC Flash, 512KX8, 55ns, PQCC32, ROHS COMPLIANT, PLASTIC, LCC-32

获取价格

A29040CL-70F AMICC Flash, 512KX8, 70ns, PQCC32, ROHS COMPLIANT, PLASTIC, LCC-32

获取价格

A29040CV-55F AMICC Flash, 512KX8, 55ns, PDSO32, 8 X 20 MM, ROHS COMPLIANT, TSOP1-32

获取价格

A29040CV-55UF AMICC Flash, 512KX8, 55ns, PDSO32, 8 X 20 MM, ROHS COMPLIANT, TSOP1-32

获取价格

A29040D AMICC 512K X 8 Bit CMOS 5.0 Volt-only,Uniform Sector Flash Memory

获取价格

A29040D-55F AMICC 512K X 8 Bit CMOS 5.0 Volt-only,Uniform Sector Flash Memory

获取价格