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A290011TY-70F PDF预览

A290011TY-70F

更新时间: 2024-02-21 10:08:50
品牌 Logo 应用领域
联笙电子 - AMICC 光电二极管内存集成电路
页数 文件大小 规格书
39页 441K
描述
Flash, 128KX8, 70ns, PDSO32, 8 X 14 MM, LEAD FREE, STSOP1-32

A290011TY-70F 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
零件包装代码:TSOP1包装说明:8 X 14 MM, LEAD FREE, STSOP1-32
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.54最长访问时间:70 ns
其他特性:TOP BOOT SECTOR启动块:TOP
命令用户界面:YES数据轮询:YES
JESD-30 代码:R-PDSO-G32长度:12.4 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
部门数/规模:1,2,1,3端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP32,.56,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
电源:5 V编程电压:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
部门规模:8K,4K,16K,32K最大待机电流:0.000005 A
子类别:Flash Memories最大压摆率:0.04 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL切换位:YES
类型:NOR TYPE宽度:8 mm
Base Number Matches:1

A290011TY-70F 数据手册

 浏览型号A290011TY-70F的Datasheet PDF文件第6页浏览型号A290011TY-70F的Datasheet PDF文件第7页浏览型号A290011TY-70F的Datasheet PDF文件第8页浏览型号A290011TY-70F的Datasheet PDF文件第10页浏览型号A290011TY-70F的Datasheet PDF文件第11页浏览型号A290011TY-70F的Datasheet PDF文件第12页 
A29001/A290011 Series  
Command Definitions  
Autoselect Command Sequence  
Writing specific address and data commands or  
sequences into the command register initiates device  
operations. The Command Definitions table defines the  
valid register command sequences. Writing incorrect  
address and data values or writing them in the improper  
sequence resets the device to reading array data.  
The autoselect command sequence allows the host  
system to access the manufacturer and devices codes,  
and determine whether or not a sector is protected. The  
Command Definitions table shows the address and data  
requirements. This method is an alternative to that shown  
in the Autoselect Codes (High Voltage Method) table,  
which is intended for PROM programmers and requires  
VID on address bit A9.  
The autoselect command sequence is initiated by writing  
two unlock cycles, followed by the autoselect command.  
The device then enters the autoselect mode, and the  
system may read at any address any number of times,  
without initiating another command sequence.  
A read cycle at address XX00h retrieves the manufacturer  
code and another read cycle at XX03h retrieves the  
continuation code. A read cycle at address XX01h returns  
the device code. A read cycle containing a sector address  
(SA) and the address 02h in returns 01h if that sector is  
protected, or 00h if it is unprotected. Refer to the Sector  
Address tables for valid sector addresses.  
All addresses are latched on the falling edge of  
or  
WE  
, whichever happens later. All data is latched on the  
CE  
rising edge of  
or  
, whichever happens first. Refer  
WE  
CE  
to the appropriate timing diagrams in the "AC  
Characteristics" section.  
Reading Array Data  
The device is automatically set to reading array data after  
device power-up. No commands are required to retrieve  
data. The device is also ready to read array data after  
completing an Embedded Program or Embedded Erase  
algorithm. After the device accepts an Erase Suspend  
command, the device enters the Erase Suspend mode.  
The system can read array data using the standard read  
timings, except that if it reads at an address within erase-  
suspended sectors, the device outputs status data. After  
The system must write the reset command to exit the  
autoselect mode and return to reading array data.  
Byte Program Command Sequence  
completing  
a programming operation in the Erase  
Suspend mode, the system may once again read array  
data with the same exception. See "Erase Suspend/Erase  
Resume Commands" for more information on this mode.  
The system must issue the reset command to re-enable  
the device for reading array data if I/O5 goes high, or while  
in the autoselect mode. See the "Reset Command"  
section, next.  
See also "Requirements for Reading Array Data" in the  
"Device Bus Operations" section for more information. The  
Read Operations table provides the read parameters, and  
Read Operation Timings diagram shows the timing  
diagram.  
Programming is a four-bus-cycle operation. The program  
command sequence is initiated by writing two unlock write  
cycles, followed by the program set-up command. The  
program address and data are written next, which in turn  
initiate the Embedded Program algorithm. The system is  
not required to provide further controls or timings. The  
device automatically provides internally generated  
program pulses and verify the programmed cell margin.  
The Command Definitions table shows the address and  
data requirements for the byte program command  
sequence.  
When the Embedded Program algorithm is complete, the  
device then returns to reading array data and addresses  
are no longer latched. The system can determine the  
status of the program operation by using I/O7 or I/O6. See  
"Write Operation Status" for information on these status  
bits.  
Reset Command  
Writing the reset command to the device resets the device  
to reading array data. Address bits are don't care for this  
command. The reset command may be written between  
the sequence cycles in an erase command sequence  
before erasing begins. This resets the device to reading  
array data. Once erasure begins, however, the device  
ignores reset commands until the operation is complete.  
The reset command may be written between the  
sequence cycles in a program command sequence before  
programming begins. This resets the device to reading  
array data (also applies to programming in Erase Suspend  
mode). Once programming begins, however, the device  
ignores reset commands until the operation is complete.  
The reset command may be written between the  
sequence cycles in an autoselect command sequence.  
Once in the autoselect mode, the reset command must be  
written to return to reading array data (also applies to  
autoselect during Erase Suspend).  
Any commands written to the device during the Embedded  
Program Algorithm are ignored. Programming is allowed in  
any sequence and across sector boundaries. A bit cannot  
be programmed from a "0" back to a "1 ". Attempting to do  
so may halt the operation and set I/O5 to "1", or cause the  
Polling algorithm to indicate the operation was  
Data  
successful. However, a succeeding read will show that the  
data is still "0". Only erase operations can convert a "0" to  
a "1".  
If I/O5 goes high during a program or erase operation,  
writing the reset command returns the device to reading  
array data (also applies during Erase Suspend).  
(May, 2012, Version 1.7)  
8
AMIC Technology, Corp.  

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