Datasheet > A290011TY-70F

A290011TY-70F

更新时间： 2024-01-26 23:20:21

品牌	Logo	应用领域
联笙电子 - AMICC		光电二极管内存集成电路
页数	文件大小	规格书
39页	441K
描述
Flash, 128KX8, 70ns, PDSO32, 8 X 14 MM, LEAD FREE, STSOP1-32

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

A290011TY-70F 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
零件包装代码：	TSOP1	包装说明：	8 X 14 MM, LEAD FREE, STSOP1-32
针数：	32	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.54	最长访问时间：	70 ns
其他特性：	TOP BOOT SECTOR	启动块：	TOP
命令用户界面：	YES	数据轮询：	YES
JESD-30 代码：	R-PDSO-G32	长度：	12.4 mm
内存密度：	1048576 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
部门数/规模：	1,2,1,3	端子数量：	32
字数：	131072 words	字数代码：	128000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP1
封装等效代码：	TSSOP32,.56,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	并行/串行：	PARALLEL
电源：	5 V	编程电压：	5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
部门规模：	8K,4K,16K,32K	最大待机电流：	0.000005 A
子类别：	Flash Memories	最大压摆率：	0.04 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	切换位：	YES
类型：	NOR TYPE	宽度：	8 mm
Base Number Matches：	1

A290011TY-70F 数据手册

A29001/A290011 Series

Standby Mode

Requirements for Reading Array Data

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs

are placed in the high impedance state, independent of the

To read array data from the outputs, the system must drive

the

and

pins to VIL.

is the power control and

selects the device.

is the output control and gates

array data to the output pins.

should remain at VIH all

input.

the time during read operation. The internal state machine

is set for reading array data upon device power-up, or after

a hardware reset. This ensures that no spurious alteration

of the memory content occurs during the power transition.

No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert

valid addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See "Reading Array Data" for more information. Refer to

the AC Read Operations table for timing specifications and

to the Read Operations Timings diagram for the timing

waveforms, l^CC1in the DC Characteristics table represents

the active current specification for reading array data.

The device enters the CMOS standby mode when the

only on A290011) are both held at

pins (

RESET

V^CC± 0.5V. (Note that this is a more restricted voltage

range than V^IH.) The device enters the TTL standby mode

when

is held at VIH, while

(Not available on

RESET

A290011) is held at VCC±0.5V. The device requires the

standard access time (t^CE) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

ICC3 in the DC Characteristics tables represents the

standby current specification.

Output Disable Mode

Writing Commands/Command Sequences

When the

input is at VIH, output from the device is

disabled. The output pins are placed in the high impedance

state.

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive

and

: Hardware Reset Pin (N/A on A290011)

RESET

to VIL, and

to VIH. An erase operation can erase one

The

pin provides a hardware method of resetting

RESET

the device to reading array data. When the system drives

the pin low for at least a period of tRP, the device

sector, multiple sectors, or the entire device. The Sector

Address Tables indicate the address range that each

sector occupies. A "sector address" consists of the address

inputs required to uniquely select a sector. See the

"Command Definitions" section for details on erasing a

sector or the entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can

then read autoselect codes from the internal register

(which is separate from the memory array) on I/O⁷- I/O0.

Standard read cycle timings apply in this mode. Refer to

the "Autoselect Mode" and "Autoselect Command

Sequence" sections for more information.

RESET

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

the duration of the

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated once

the device is ready to accept another command sequence,

to ensure data integrity.

pulse. The device also resets

RESET

The

pin may be tied to the system reset circuitry.

RESET

A system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

Refer to the AC Characteristics tables for

parameters and diagram.

ICC2 in the Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

RESET

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O7 - I/O0. Standard read cycle timings and ICC read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section

for timing diagrams.

(May, 2012, Version 1.7)

AMIC Technology, Corp.

1...3 4 567 8 9...39

下载PDF

与A290011TY-70F相关器件

型号	品牌	描述	获取价格	数据表
A290011TY-90	AMICC	Flash, 128KX8, 90ns, PDSO32, 8 X 14 MM, STSOP1-32	获取价格
A290011TY-90F	AMICC	Flash, 128KX8, 90ns, PDSO32, 8 X 14 MM, LEAD FREE, STSOP1-32	获取价格
A290011U-55	AMICC	128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A290011U-55F	AMICC	128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A290011U-70	AMICC	128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A290011U-70F	AMICC	128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格

与A290011TY-70F相关文章

深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

4
74HC573三态非易失锁存器(Latch)资料手册参数分析
2024-05-10

3
MAX3232 RS-232电平转换器资料手册参数分析
2024-05-10

4
MAX485 RS-485/RS-422收发器资料手册参数分析
2024-05-10

4

产品中心

服务支持

精选活动

关于我们

帮助中心

A290011TY-70F

A290011TY-70F 技术参数

A290011TY-70F 数据手册

与A290011TY-70F相关器件

与A290011TY-70F相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

A290011TY-70F

A290011TY-70F 技术参数

A290011TY-70F 数据手册

与A290011TY-70F相关器件

与A290011TY-70F相关文章

您还可以找

您在本页遇到什么问题？