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A290011TY-70F PDF预览

A290011TY-70F

更新时间: 2024-01-10 16:47:54
品牌 Logo 应用领域
联笙电子 - AMICC 光电二极管内存集成电路
页数 文件大小 规格书
39页 441K
描述
Flash, 128KX8, 70ns, PDSO32, 8 X 14 MM, LEAD FREE, STSOP1-32

A290011TY-70F 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
零件包装代码:TSOP1包装说明:8 X 14 MM, LEAD FREE, STSOP1-32
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.54最长访问时间:70 ns
其他特性:TOP BOOT SECTOR启动块:TOP
命令用户界面:YES数据轮询:YES
JESD-30 代码:R-PDSO-G32长度:12.4 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
部门数/规模:1,2,1,3端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP32,.56,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
电源:5 V编程电压:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
部门规模:8K,4K,16K,32K最大待机电流:0.000005 A
子类别:Flash Memories最大压摆率:0.04 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL切换位:YES
类型:NOR TYPE宽度:8 mm
Base Number Matches:1

A290011TY-70F 数据手册

 浏览型号A290011TY-70F的Datasheet PDF文件第5页浏览型号A290011TY-70F的Datasheet PDF文件第6页浏览型号A290011TY-70F的Datasheet PDF文件第7页浏览型号A290011TY-70F的Datasheet PDF文件第9页浏览型号A290011TY-70F的Datasheet PDF文件第10页浏览型号A290011TY-70F的Datasheet PDF文件第11页 
A29001/A290011 Series  
Sector Protection/Unprotection  
The hardware sector protection feature disables both  
program and erase operations in any sector. The  
hardware sector unprotection feature re-enables both  
program and erase operations in previously protected  
sectors.  
START  
Sector protection/unprotection must be implemented using  
programming equipment. The procedure requires a high  
voltage (VID) on address pin A9 and the control pins.  
The device is shipped with all sectors unprotected.  
It is possible to determine whether a sector is protected or  
unprotected. See "Autoselect Mode" for details.  
RESET = VID  
(Note 1)  
Hardware Data Protection  
Perform Erase or  
The requirement of command unlocking sequence for  
programming or erasing provides data protection against  
inadvertent writes (refer to the Command Definitions  
table). In addition, the following hardware data protection  
measures prevent accidental erasure or programming,  
which might otherwise be caused by spurious system level  
signals during VCC power-up transitions, or from system  
noise. The device is powered up to read array data to  
avoid accidentally writing data to the array.  
Program Operations  
RESET = VIH  
Write Pulse "Glitch" Protection  
Noise pulses of less than 5ns (typical) on  
,
or  
OE CE  
Temporary Sector  
Unprotect  
do not initiate a write cycle.  
WE  
Completed (Note 2)  
Logical Inhibit  
Write cycles are inhibited by holding any one of  
=VIL,  
OE  
CE  
= VIH or  
= VIH. To initiate a write cycle,  
and  
WE  
CE  
Notes:  
must be a logical zero while  
is a logical one.  
OE  
WE  
1. All protected sectors unprotected.  
2. All previously protected sectors are protected once again.  
Power-Up Write Inhibit  
If  
=
= VIL and  
= VIH during power up, the  
OE  
WE CE  
device does not accept commands on the rising edge of  
. The internal state machine is automatically reset to  
Figure 1. Temporary Sector Unprotect Operation  
WE  
reading array data on the initial power-up.  
Temporary Sector Unprotect (N/A A290011)  
This feature allows temporary unprotection of previous  
protected sectors to change data in-system. The Sector  
Unprotect mode is activated by setting the  
pin to  
RESET  
VID. During this mode, formerly protected sectors can be  
programmed or erased by selecting the sector addresses.  
Once VID is removed from the  
pin, all the  
RESET  
previously protected sectors are protected again. Figure 1  
shows the algorithm, and the Temporary Sector Unprotect  
diagram shows the timing waveforms, for this feature.  
(May, 2012, Version 1.7)  
7
AMIC Technology, Corp.  

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