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A25S16M8VR-X

更新时间： 2022-02-26 12:26:39

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A25S16M8VR-X 数据手册

A25S16

MEMORY

AiT Semiconductor Inc.

www.ait-ic.com

16M BIT SPI NOR FLASH

32KB Block Erase (52H)

The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction

must previously have been executed to set the Write Enable Latch bit. The 32KB Block Erase instruction is

entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the

block is a valid address for the 32KB Block Erase instruction. /CS must be driven low for the entire duration of

the sequence.

See Figure 31, the 32KB Block Erase instruction sequence: /CS goes low sending 32KB Block Erase

instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address

byte has been latched in; otherwise the 32KB Block Erase instruction is not executed. As soon as /CS is

driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle

is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 32KB Block Erase

instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) bits (see

Table 5&6) is not executed.

Figure 31. 32KB Block Erase Sequence Diagram

REV1.0

- JUN 2015 RELEASED -

- 46 -

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