Datasheet > A25L16PMF-50F

A25L16PMF-50F

更新时间： 2022-11-29 02:46:31

品牌	Logo	应用领域
联笙电子 - AMICC		闪存
页数	文件大小	规格书
34页	514K
描述
8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface

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A25L16PMF-50F 数据手册

A25L80P

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 4.) sets the Write

Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every

Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and

Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving

Chip Select ( ) Low, sending the instruction code, and then

driving Chip Select ( ) High.

Figure 4. Write Enable (WREN) Instruction Sequence

Instruction

High Impedance

Write Disable (WRDI)

﹣ Power-up

The Write Disable (WRDI) instruction (Figure 5.) resets the

﹣ Write Disable (WRDI) instruction completion

﹣ Write Status Register (WRSR) instruction completion

﹣ Page Program (PP) instruction completion

﹣ Sector Erase (SE) instruction completion

﹣ Bulk Erase (BE) instruction completion

Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip

Select ( ) Low, sending the instruction code, and then driving

Chip The Write Enable Latch (WEL) bit is reset under the

following conditions:

Figure 5. Write Disable (WRDI) Instruction Sequence

Instruction

High Impedance

PRELIMINARY (May 2005, Version 0.0)

AMIC Technology Corp.

1...7 8 91011 12 13...34

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型号	品牌	描述	获取价格	数据表
A25L16PMF-50U	AMICC	8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface	获取价格
A25L16PMF-50UF	AMICC	8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface	获取价格
A25L16PM-U	AMICC	Flash, 16MX1, PDSO8, 0.209 INCH, SOP-8	获取价格
A25L16PM-UF	AMICC	Flash, 16MX1, PDSO8, 0.209 INCH, LEAD FREE, SOP-8	获取价格
A25L16PMW-50	AMICC	8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface	获取价格
A25L16PMW-50F	AMICC	8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface	获取价格