Datasheet > A14V100A

A14V100A

更新时间： 2024-11-16 12:55:39

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
90页	4501K
描述
Accelerator Series FPGAs â ACT 3 Family

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A14V100A 数据手册

Revision 3

Accelerator Series FPGAs – ACT 3 Family

• More than 500 Macro Functions

Features

• Replaces up to Twenty 32 Macro-Cell CPLDs

• Up to 10,000 Gate Array Equivalent Gates (up to 25,000

equivalent PLD Gates)

• Replaces up to One Hundred 20-Pin PAL^®Packages

• Up to 1,153 Dedicated Flip-Flops

• VQFP, TQFP, BGA, and PQFP Packages

• Nonvolatile, User Programmable

• Fully Tested Prior to Shipment

• 5.0 V and 3.3 V Versions

• Optimized for Logic Synthesis Methodologies

• Low Power CMOS Technology

• Highly Predictable Performance with 100% Automatic Place-

and-Route

• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)

• Up to 186 MHz On-Chip Performance (–1 Speed Grade)

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

Table 1 • ACT 3 Family Product Information

Device

A1415

A1425

A1440

A1460

A14100

Capacity

Gate Array Equivalent Gates

1,500

3,750

2,500

6,250

4,000

10,000

100

6,000

15,000

150

10,000

25,000

250

PLD Equivalent Gates

TTL Equivalent Package (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

Logic Modules

100

200

104

310

160

150

360

100

564

848

1,377

697

S-Module

288

432

C-Module

Dedicated Flip-Flops¹

276

416

680

264

568

768

1,153

228

User I/Os (maximum)

140

168

Maximum Performance²(worst-case commercial, –1 speed grade)

Chip-to-Chip³(MHz)

Accumulators (16-bit, MHz)

Loadable Counter (16-bit, MHz)

Prescaled Loadable Counters (16-bit, MHz)

Datapath, Shift Registers (MHz)

Clock-to-Output (pad-to-pad, ns)

Packages⁴(by pin count)

186

9.0

186

9.0

186

9.5

150

10.0

150

10.5

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

PG100⁵

PL84

PQ100

–

PG133⁵

PL84

PQ100, PQ160

PG175⁵

PL84

PQ160

–

VQ100

TQ176

–

PG207

PG257

–

PQ160, PQ208

–

VQ100

–

RQ208

–

VQ100

–

TQ176

BG225⁵

CQ196

–

BG313

CQ256

CQFP

CQ132

–

Notes:

1. One flip-flop per S0Module, two flip-flops per I/O Module.

2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.

3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the "System Performance Model" on page 1-1 and

Table 1-1 on page 1-2.

4. See the "Product Plan" table on page III for package availability.

5. Discontinued device and package combination.

6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product

Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:

PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004

January 2012

12 3 4 5 6 7...90

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与A14V100A相关器件

型号	品牌	获取价格	描述	数据表
A14V100AA-1BG208B	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1BG208C	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1BG208I	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1BG208M	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1CQ208B	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1CQ208C	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1CQ208I	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1CQ208M	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1PG208B	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family
A14V100AA-1PG208C	ACTEL	获取价格	Accelerator Series FPGAs - ACT 3Family

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