Datasheet > A1225XL-2PQ100I

A1225XL-2PQ100I

更新时间： 2024-01-18 12:34:33

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
84页	4582K
描述
Field Programmable Gate Array, 200MHz, 451-Cell, CMOS, PQFP100,

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技术参数
数据手册

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A1225XL-2PQ100I 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, QFP-100	Reach Compliance Code：	compliant
风险等级：	5.81	其他特性：	MAX 83 I/OS
最大时钟频率：	225 MHz	CLB-Max的组合延迟：	2.6 ns
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	湿度敏感等级：	3
可配置逻辑块数量：	451	等效关口数量：	2500
输入次数：	83	逻辑单元数量：	451
输出次数：	83	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	451 CLBS, 2500 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	225	电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm

A1225XL-2PQ100I 数据手册

Integrator Series FPGAs: 1200XL and 3200DX Families

such as FIFOs, LIFOs, and RAM arrays. Additionally, unused

SRAM blocks can be used to implement registers for other

logic within the design.

be joined together at the ends using antifuses to increase

their lengths up to the full length of the track. All

interconnects can be accomplished with a maximum of four

antifuses.

I/O Modules

Horizontal Routing

The I/O modules provide the interface between the device

pins and the logic array. Figure 5 is a block diagram of the

I/O module. A variety of user functions, determined by a

library macro selection, can be implemented in the module

(refer to the Macro Library Guide for more information). I/O

modules contain a tri-state buffer, input and output latches

which can be configured for input, output, or bi-directional

pins (Figure 5).

Horizontal channels are located between the rows of

modules and are composed of several routing tracks. The

horizontal routing tracks within the channel are divided

into one or more segments. The minimum horizontal

segment length is the width of a module pair, and the

maximum horizontal segment length is the full length of the

channel. Any segment that spans more than one-third the

row length is considered a long horizontal segment. A

typical channel is shown in Figure 6. Non-dedicated

horizontal routing tracks are used to route signal nets;

dedicated routing tracks are used for the global clock

networks and for power and ground tie-off tracks.

Vertical Routing

PAD

From Array

Another set of routing tracks run vertically through the

module. Vertical tracks are of three types: input, output, and

long, and are divided into one or more segments. Each

segment in an input track is dedicated to the input of a

particular module; each segment in an output track is

dedicated to the output of a particular module. Long

segments are uncommitted and can be assigned during

routing. Each output segment spans four channels (two

above and two below), except near the top and bottom of the

array where edge effects occur. Long Vertical Tracks contain

either one or two segments. An example of vertical routing

tracks and segments is shown in Figure 6.

G/CLK*

To Array

G/CLK*

* Can be Configured as a Latch or D Flip-Flop

(Using C-Module)

Figure 5 • I/O Module

Segmented

Logic

Horizontal

Modules

The Integrator Series devices contain flexible I/O structures

where each output pin has a dedicated output enable

control. The I/O module can be used to latch input and/or

output data, providing a fast set-up time. In addition, the

Actel Designer Series software tools can build a D-type

flip-flop using a C-module to register input and/or output

signals.

Routing

Tracks

Antifuses

Actel’s Designer Series development tools provide a design

library of I/O macrofunctions which can implement all I/O

configurations supported by the Integrator Series FPGAs.

Vertical Routing Tracks

Routing Structure

Figure 6 • Routing Structure

The Integrator Series architecture uses vertical and

horizontal routing tracks to interconnect the various logic

and I/O modules. These routing tracks are metal

interconnects that may either be of continuous length or

broken into pieces called segments. Varying segment

lengths allows interconnection of over 90% of design tracks

to occur with only two antifuse connections. Segments can

Antifuse Structure

An antifuse is a “normally open” structure as opposed to the

normally closed fuse structure used in PROMs or PALs. The

use of antifuses to implement a programmable logic device

results in highly-testable structures as well as efficient

Discontinued – v3.0

1...5 6 789 10 11...84

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与A1225XL-2PQ100I相关器件

型号	品牌	描述	获取价格	数据表
A1225XL-2PQ100IX79	ACTEL	Field Programmable Gate Array, 202.7MHz, 451-Cell, CMOS, PQFP100,	获取价格
A1225XL-2PQG100C	ACTEL	Field Programmable Gate Array, 225MHz, 451-Cell, CMOS, PQFP100	获取价格
A1225XL-2PQG100I	ACTEL	Field Programmable Gate Array, 202.7MHz, 451-Cell, CMOS, PQFP100	获取价格
A1225XL-2VQ100C	ACTEL	Field Programmable Gate Array, 451 CLBs, 2500 Gates, 225MHz, 451-Cell, CMOS, PQFP100, 1 MM	获取价格
A1225XL-2VQ100C	MICROSEMI	Field Programmable Gate Array, 200MHz, 451-Cell, CMOS, PQFP100,	获取价格
A1225XL-2VQ100CX79	ACTEL	Field Programmable Gate Array, 225MHz, 451-Cell, CMOS, PQFP100,	获取价格

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