Datasheet > A1225XL-2PQ100I

A1225XL-2PQ100I

更新时间： 2024-01-07 09:46:05

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
84页	4582K
描述
Field Programmable Gate Array, 200MHz, 451-Cell, CMOS, PQFP100,

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A1225XL-2PQ100I 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, QFP-100	Reach Compliance Code：	compliant
风险等级：	5.81	其他特性：	MAX 83 I/OS
最大时钟频率：	225 MHz	CLB-Max的组合延迟：	2.6 ns
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	湿度敏感等级：	3
可配置逻辑块数量：	451	等效关口数量：	2500
输入次数：	83	逻辑单元数量：	451
输出次数：	83	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	451 CLBS, 2500 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	225	电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm

A1225XL-2PQ100I 数据手册

Integrator Series FPGAs: 1200XL and 3200DX Families

3200DX devices contain a third type of logic module,

D-modules, which are arranged around the periphery of the

device. D-modules contain wide-decode circuitry which

provides a fast, wide-input AND function similar to that

found in product term architectures (Figure 3). The

D-module allows 3200DX devices to perform wide-decode

functions at speeds comparable CPLDs and PAL devices.

The output of the D-module has a programmable inverter

for active HIGH or LOW assertion. The D-module output is

hard-wired to an output pin or can be fed back into the

array to be incorporated into other logic.

modules can be cascaded together to form memory spaces

of user-definable width and depth. A block diagram of the

3200DX dual-port SRAM block is shown in Figure 4.

7 Inputs

Hard-Wire to I/O

Programmable

Inverter

Dual-Port SRAM Modules

Several 3200DX devices contain dual-port SRAM modules

that have been optimized for synchronous or asynchronous

applications. The SRAM modules are arranged in 256-bit

blocks which can be configured as 32x8 or 64x4 (refer to

“Integrator Series Product Profile Family” on page 1 for the

number of SRAM blocks within a particular device). SRAM

Feedback to Array

Figure 3 • D-Module Implementation

WD[7:0]

Latches

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4

Latches

Read

Port

Logic

Write

Port

Logic

(256 Bits)

WRAD[5:0]

[5:0]

Read

Logic

Latches

REN

RCLK

MODE

BLKEN

WEN

RD[7:0]

Write

Logic

Routing Tracks

WCLK

Figure 4 • 3200DX Dual-Port SRAM Block

The 3200DX SRAM modules are true dual-port structures

containing independent READ and WRITE ports. Each

SRAM module contains six bits of read and write addressing

(RDAD[5:0] and WRAD[5:0], respectively) for 64x4 bit

blocks. When configured in byte mode, the highest order

address bits (RDAD5 and WRAD5) are not used. The read

and write ports of the SRAM block contain independent

clocks (RCLK and WCLK) with programmable polarities

offering active HIGH or LOW implementation. The SRAM

block contains eight data inputs (WD[7:0]) and eight

outputs (RD[7:0]) which are connected to segmented

vertical routing tracks.

The 3200DX dual-port SRAM blocks provide an optimal

solution for high-speed buffered applications requiring fast

FIFO and LIFO queues. Actel’s ACTgen Macro Builder

provides the capability to quickly design memory functions,

Discontinued – v3.0

1...4 5 678 9 10...84

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与A1225XL-2PQ100I相关器件

型号	品牌	描述	获取价格	数据表
A1225XL-2PQ100IX79	ACTEL	Field Programmable Gate Array, 202.7MHz, 451-Cell, CMOS, PQFP100,	获取价格
A1225XL-2PQG100C	ACTEL	Field Programmable Gate Array, 225MHz, 451-Cell, CMOS, PQFP100	获取价格
A1225XL-2PQG100I	ACTEL	Field Programmable Gate Array, 202.7MHz, 451-Cell, CMOS, PQFP100	获取价格
A1225XL-2VQ100C	ACTEL	Field Programmable Gate Array, 451 CLBs, 2500 Gates, 225MHz, 451-Cell, CMOS, PQFP100, 1 MM	获取价格
A1225XL-2VQ100C	MICROSEMI	Field Programmable Gate Array, 200MHz, 451-Cell, CMOS, PQFP100,	获取价格
A1225XL-2VQ100CX79	ACTEL	Field Programmable Gate Array, 225MHz, 451-Cell, CMOS, PQFP100,	获取价格

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