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A1020B-VQ80C PDF预览

A1020B-VQ80C

更新时间： 2024-02-05 00:34:30
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
24页 159K
描述
Field Programmable Gate Array, 547 CLBs, 2000 Gates, 45MHz, 547-Cell, CMOS, PQFP80, 1 MM, VQFP-80

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A1020B-VQ80C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：1 MM, VQFP-80
针数：80Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.9
其他特性：MAX 69 I/OS最大时钟频率：45 MHz
CLB-Max的组合延迟：4.5 nsJESD-30 代码：S-PQFP-G80
JESD-609代码：e0长度：14 mm
湿度敏感等级：3可配置逻辑块数量：547
等效关口数量：2000输入次数：69
逻辑单元数量：547输出次数：69
端子数量：80最高工作温度：70 °C
最低工作温度：组织：547 CLBS, 2000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装等效代码：TQFP80,.6SQ封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE峰值回流温度（摄氏度）：225
电源：5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Field Programmable Gate Arrays最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

A1020B-VQ80C 数据手册

 浏览型号A1020B-VQ80C的Datasheet PDF文件第7页浏览型号A1020B-VQ80C的Datasheet PDF文件第8页浏览型号A1020B-VQ80C的Datasheet PDF文件第9页浏览型号A1020B-VQ80C的Datasheet PDF文件第11页浏览型号A1020B-VQ80C的Datasheet PDF文件第12页浏览型号A1020B-VQ80C的Datasheet PDF文件第13页 
A C T 1 T i m i n g M o d u l e *  
Input Delay  
Internal Delays  
Predicted  
Routing  
Delays  
Output Delay  
I/O Module  
I/O Module  
Logic Module  
t
= 3.1 ns  
INYL  
t
t
= 1.4 ns  
IRD2  
t
= 6.7 ns  
DLH  
t
= 0.9 ns  
= 3.1 ns  
= 6.6 ns  
t
t
t
= 0.9 ns  
IRD1  
RD1  
t
t
= 2.9 ns  
= 2.9 ns  
PD  
CO  
t
= 11.6 ns  
= 1.4 ns  
= 3.1 ns  
= 6.6 ns  
ENHZ  
RD2  
IRD4  
t
IRD8  
RD4  
t
RD8  
ARRAY  
CLOCK  
t
= 5.6 ns  
FO = 128  
CKH  
F
= 70 MHz  
MAX  
* Values shown for ACT 1 ‘–3 speed’ devices at worst-case commercial conditions.  
P r e d i c t a b l e P e r f o r m a n c e : T i g h t D e l a y  
D i s t r i b u t i o n s  
T i m i n g C h a r a c t e r i s t i c s  
Timing characteristics for ACT 1 devices fall into three  
categories: family dependent, device dependent, and design  
dependent. The input and output buffer characteristics are  
common to all ACT 1 family members. Internal routing delays  
are device dependent. Design dependency means actual delays  
are not determined until after placement and routing of the  
user design is complete. Delay values may then be determined  
by using the DirectTime Analyzer utility or performing  
simulation with post-layout delays.  
Propagation delay between logic modules depends on the  
resistive and capacitive loading of the routing tracks, the  
interconnect elements, and the module inputs being driven.  
Propagation delay increases as the length of routing tracks,  
the number of interconnect elements, or the number of  
inputs increases.  
From a design perspective, the propagation delay can be  
statistically correlated or modeled by the fanout (number of  
loads) driven by a module. Higher fanout usually requires  
some paths to have longer routing tracks.  
C r it ic a l N e t s a n d T y p ic a l N e t s  
Propagation delays are expressed only for typical nets, which  
are used for initial design performance evaluation. Critical  
net delays can then be applied to the most time-critical paths.  
Critical nets are determined by net property assignment prior  
to placement and routing. Up to 6% of the nets in a design may  
be designated as critical, while 90% of the nets in a design are  
typical.  
The ACT 1 family delivers a very tight fanout delay  
distribution. This tight distribution is achieved in two ways: by  
decreasing the delay of the interconnect elements and by  
decreasing the number of interconnect elements per path.  
Actel’s patented PLICE antifuse offers a very low  
resistive/capacitive interconnect. The ACT 1 family’s  
antifuses, fabricated in 1.0 micron lithography, offer nominal  
levels of 200 ohms resistance and 7.5 femtofarad (fF)  
capacitance per antifuse.  
Lo n g T r a c k s  
Some nets in the design use long tracks. Long tracks are  
special routing resources that span multiple rows, columns, or  
modules. Long tracks employ three and sometimes four  
antifuse connections. This increases capacitance and  
resistance, resulting in longer net delays for macros  
connected to long tracks. Typically, up to 6% of nets in a fully  
utilized device require long tracks. Long tracks contribute  
approximately 5 ns to 10 ns delay. This additional delay is  
represented statistically in higher fanout (FO=8) routing  
delays in the data sheet specifications section.  
The ACT 1 fanout distribution is also tight due to the low  
number of antifuses required for each interconnect path. The  
ACT 1 family’s proprietary architecture limits the number of  
antifuses per path to a maximum of four, with 90% of  
interconnects using two antifuses.  
1 -2 9 2  
1...78910111213...24

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与A1020B-VQ80C相关器件

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A1020B-VQG80C ACTEL Field Programmable Gate Array, 547 CLBs, 2000 Gates, 45MHz, 547-Cell, CMOS, PQFP80, MO-136

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A1020B-VQG80I ACTEL Field Programmable Gate Array, 547 CLBs, 2000 Gates, CMOS, PQFP80, VQFP-80

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