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A1020B-VQ80C PDF预览

A1020B-VQ80C

更新时间： 2024-02-29 14:19:35
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
24页 159K
描述
Field Programmable Gate Array, 547 CLBs, 2000 Gates, 45MHz, 547-Cell, CMOS, PQFP80, 1 MM, VQFP-80

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A1020B-VQ80C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：1 MM, VQFP-80
针数：80Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.9
其他特性：MAX 69 I/OS最大时钟频率：45 MHz
CLB-Max的组合延迟：4.5 nsJESD-30 代码：S-PQFP-G80
JESD-609代码：e0长度：14 mm
湿度敏感等级：3可配置逻辑块数量：547
等效关口数量：2000输入次数：69
逻辑单元数量：547输出次数：69
端子数量：80最高工作温度：70 °C
最低工作温度：组织：547 CLBS, 2000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装等效代码：TQFP80,.6SQ封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE峰值回流温度（摄氏度）：225
电源：5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Field Programmable Gate Arrays最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

A1020B-VQ80C 数据手册

 浏览型号A1020B-VQ80C的Datasheet PDF文件第4页浏览型号A1020B-VQ80C的Datasheet PDF文件第5页浏览型号A1020B-VQ80C的Datasheet PDF文件第6页浏览型号A1020B-VQ80C的Datasheet PDF文件第8页浏览型号A1020B-VQ80C的Datasheet PDF文件第9页浏览型号A1020B-VQ80C的Datasheet PDF文件第10页 
™
A C T  
1 S e r i e s F P G A s  
P a c k a g e T h e r m a l C h a r a c t e r i s t i c s  
A sample calculation of the maximum power dissipation for  
an 84-pin plastic leaded chip carrier at commercial  
temperature is as follows:  
The device junction to case thermal characteristics is  
θjc, and the junction to ambient air characteristics is θja. The  
thermal characteristics for θja are shown with two different  
air flow rates. Maximum junction temperature is 150°C.  
Max junction temp.(°C) – Max commercial temp.(°C)  
150°C – 70°C  
37°C ⁄ W  
------------------------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.2 W  
θja(°C ⁄ W)  
θja  
Still Air  
θja  
300 ft/min  
Package Type  
Pin Count  
θjc  
Units  
44  
68  
84  
15  
13  
12  
45  
38  
37  
35  
29  
28  
°C/W  
°C/W  
°C/W  
Plastic J-Leaded Chip Carrier  
Plastic Quad Flatpack  
100  
80  
13  
12  
8
48  
43  
33  
40  
40  
35  
20  
30  
°C/W  
°C/W  
°C/W  
°C/W  
Very Thin (1.0 mm) Quad Flatpack  
Ceramic Pin Grid Array  
84  
Ceramic Quad Flatpack  
84  
5
G e n e r a l P o w e r E q u a t i o n  
The power due to standby current is typically a small  
component of the overall power. Standby power is calculated  
below for commercial, worst case conditions.  
P = [ICCstandby + ICCactive] * V + IOL * V * N + IOH  
*
CC  
OL  
(V – V ) * M  
CC  
OH  
ICC  
V
Power  
CC  
Where:  
3 mA  
5.25 V  
5.25 V  
3.60 V  
3.30 V  
15.75 mW (max)  
5.25 mW (typ)  
2.70 mW (max)  
0.99 mW (typ)  
ICCstandby is the current flowing when no inputs or  
outputs are changing.  
1 mA  
0.75 mA  
0.30 mA  
ICCactive is the current flowing due to CMOS switching.  
IOL, IOH are TTL sink/source currents.  
Ac t iv e P o w e r C o m p o n e n t  
V , VOH are TTL level output voltages.  
OL  
N equals the number of outputs driving TTL loads to  
Power dissipation in CMOS devices is usually dominated by  
the active (dynamic) power dissipation. This component is  
frequency dependent, a function of the logic and the  
V .  
OL  
M equals the number of outputs driving TTL loads to  
V .  
external I/O. Active power dissipation results from charging  
internal chip capacitances of the interconnect,  
unprogrammed antifuses, module inputs, and module  
outputs, plus external capacitance due to PC board traces  
and load device inputs. An additional component of the active  
power dissipation is the totem-pole current in CMOS  
transistor pairs. The net effect can be associated with an  
equivalent capacitance that can be combined with frequency  
and voltage to represent active power dissipation.  
OH  
An accurate determination of N and M is problematical  
because their values depend on the family type, design  
details, and on the system I/O. The power can be divided into  
two components: static and active.  
S t a t ic P o w e r C o m p o n e n t  
Actel FPGAs have small static power components that result  
in lower power dissipation than PALs or PLDs. By integrating  
multiple PALs/PLDs into one FPGA, an even greater  
reduction in board-level power dissipation can be achieved.  
1 -2 8 9  
1...45678910...24

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