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A1020B-PL84I

更新时间： 2024-02-23 06:44:51
品牌 Logo 应用领域
ACTEL 时钟栅可编程逻辑
页数 文件大小 规格书
24页 163K
描述
Field Programmable Gate Array, 547 CLBs, 2000 Gates, 40.5MHz, 547-Cell, CMOS, PQCC84, PLASTIC, MS-007-AE, LCC-84

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A1020B-PL84I 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：PLASTIC, MS-007-AE, LCC-84Reach Compliance Code：compliant
风险等级：5.84其他特性：MAX 69 I/OS
最大时钟频率：40.5 MHzCLB-Max的组合延迟：4.5 ns
JESD-30 代码：S-PQCC-J84JESD-609代码：e0
长度：29.21 mm湿度敏感等级：3
可配置逻辑块数量：547等效关口数量：2000
输入次数：69逻辑单元数量：547
输出次数：69端子数量：84
最高工作温度：85 °C最低工作温度：-40 °C
组织：547 CLBS, 2000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC84,1.2SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：225电源：5 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：4.45 mm子类别：Field Programmable Gate Arrays
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：29.21 mm
Base Number Matches：1

A1020B-PL84I 数据手册

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E q u iv a le n t C a p a c it a n c e  
CEQM = Equivalent capacitance of logic modules in pF  
CEQI = Equivalent capacitance of input buffers in pF  
The power dissipated by a CMOS circuit can be expressed by  
the Equation 1.  
CEQO = Equivalent capacitance of output buffers in pF  
Power (uW) = CEQ * VCC2 * F  
(1)  
CEQCR = Equivalent capacitance of routed array clock in  
pF  
Where:  
CEQ is the equivalent capacitance expressed in pF.  
CL  
fm  
fn  
= Output lead capacitance in pF  
V is the power supply in volts.  
= Average logic module switching rate in MHz  
= Average input buffer switching rate in MHz  
= Average output buffer switching rate in MHz  
CC  
F is the switching frequency in MHz.  
Equivalent capacitance is calculated by measuring ICCactive  
at a specified frequency and voltage for each circuit  
component of interest. Measurements have been made over a  
fp  
fq1  
= Average first routed array clock rate in MHz (All  
families)  
range of frequencies at a fixed value of V . Equivalent  
CC  
capacitance is frequency independent so that the results may  
be used over a wide range of operating conditions. Equivalent  
capacitance values are shown below.  
F ix e d C a p a c it a n c e Va lu e s fo r Ac t e l F P G As  
(p F )  
r1  
C
Va lu e s fo r Ac t e l F P G As  
E Q  
Device Type  
A1010B  
routed_Clk1  
41.4  
68.6  
40  
A10V10B  
A10V20B  
A1010B  
A1020B  
A1020B  
Modules (CEQM  
Input Buffers (CEQI  
Output Buffers (CEQO  
Routed Array Clock Buffer  
Loads (CEQCR  
)
3.2  
10.9  
11.6  
3.7  
22.1  
31.2  
A10V10B  
A10V20B  
)
65  
)
De t e r m in in g Av e r a g e S w it c h in g F r e q u e n c y  
To determine the switching frequency for a design, you must  
have a detailed understanding of the data input values to the  
circuit. The following guidelines are meant to represent  
worst-case scenarios so that they can be generally used to  
predict the upper limits of power dissipation. These  
guidelines are as follows:  
)
4.1  
4.6  
To calculate the active power dissipated from the complete  
design, the switching frequency of each part of the logic must  
be known. Equation 2 shows a piece-wise linear summation  
over all components.  
Logic Modules (m)  
90% of modules  
#inputs/4  
Power = V 2 * [(m * CEQM * fm)modules  
+
CC  
Inputs switching (n)  
(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs  
0.5 * (q1 * CEQCR * fq1)routed_Clk1  
(r1 * fq1)routed_Clk1  
+
Outputs switching (p)  
First routed array clock loads (q1)  
Load capacitance (CL)  
#outputs/4  
40% of modules  
35 pF  
+
]
(2)  
Where:  
Average logic module switching rate (fm) F/10  
m
n
= Number of logic modules switching at fm  
= Number of input buffers switching at fn  
= Number of output buffers switching at fp  
Average input switching rate (fn)  
Average output switching rate (fp)  
F/5  
F/10  
p
Average first routed array clock rate F  
(fq1)  
q1  
= Number of clock loads on the first routed array  
clock (All families)  
r1  
= Fixed capacitance due to first routed array  
clock (All families)  
1 -2 9 0  
1...567891011...24

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