9ZXL06x2E/9ZXL08xxE/9ZXL12x2E Datasheet
2.4
9ZXL12x2E Pin Assignments
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA 1
GNDA 2
48 GND
47 DIF7#
46 DIF7
45 vOE7#
44 vOE6#
43 DIF6#
42 DIF6
41 GND
40 VDD
39 DIF5#
38 DIF5
37 vOE5#
36 vOE4#
35 DIF4#
34 DIF4
33 GND
vSMB_WRTLOCK 3
^100M_133M# 4
^HIBW_BYPM_LOBW# 5
^CKPWRGD_PD# 6
GNDR 7
9ZXL1232
9ZXL1252
Connect EPAD to ground
VDDR 8
DIF_IN 9
DIF_IN# 10
vSADR0_tri 11
SMBDAT 12
SMBCLK 13
vSADR1_tri 14
FBOUT_NC# 15
FBOUT_NC 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9 × 9 mm, 0.5mm pitch 64-VFQFPN
Pins with ^ prefix have internal 120kohm pull-up
Pins with v prefix have internal 120kohm pull-down
Figure 4. Pin Assignment for 9 × 9 mm 64-VFQFPN Package – Top View
2.5
Pin Descriptions
Table 1. Pin Descriptions
9ZXL12x2 9ZXL08x2 9ZXL0853 9ZXL06x2
Name
Type
Description
Pin No.
Pin No.
Pin No.
Pin No.
3.3V Input to select operating frequency. This pin
Latched has an internal pull-up resistor. See
^100M_133M#
4
47
47
-
In
<Hyperlink>Frequency Selection (PLL Mode) table
for definition.
Input notifies device to sample latched inputs and
start up on first high assertion. Low enters Power
^CKPWRGD_PD# Input Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up
resistor.
6
1
1
3
R31DS0159EU0102 Rev.1.02
Dec 22, 2022
Page 7