16-bit Microcontrollers
MC9S12DG256
Target Applications
Features
Benefits
> Automotive applications
> Industrial control
High-Performance 16-bit HCS12 CPU Core
> 25 MHz bus operation at 5V for 40 ns
minimum instruction cycle time
> Opcode compatible with the 68HC11
and 68HC12
> C-optimized architecture produces extremely
compact code
On-Chip Debug Interface
> Dedicated serial debug interface
> Real-time in-circuit emulation and debug
without expensive and cumbersome
box emulators
> On-chip breakpoints
> Read/write memory and registers while running
at full speed
Overview
Freescale Semiconductor’s HCS12 Family of
microcontrollers (MCUs) is the next generation of
the highly successful 68HC12 architecture. Using
Freescale’s industry-leading 0.25 µs Flash, the
MC9S12DG256 is part of a pin-compatible
family that scales from 32 KB to 512 KB of Flash
memory. The MC9S12DG256 provides an upward
migration path from Freescale’s 68HC08, 68HC11
and 68HC12 architectures for applications that
need larger memory, more peripherals and higher
performance. Also, with the increasing number of
CAN-based electronic control units (ECUs), its
multiple network modules support this environment
by enabling highly efficient communications
between different network buses.
Network Modules
> Two msCAN modules implementing the CAN
2.0 A/B protocol
> Ability to link modules for higher
buffer count
• Five receive buffers per module with FIFO
storage scheme
> Programmable bit rate up to 1 Mbps
> FIFO receive approach superior for
event-driven networks
• Three transmit buffers per module with
internal prioritization
Integrated Third-Generation Flash Memory
> In-application reprogrammable
> Flexibility to change code in the field
> Efficient end-of-line programming
> Self-timed, fast programming
• Fast Flash page erase—20 ms
(512 bytes)
> Total program time for 256 KB code is less
than 10 seconds
• Can program 16 bits in 20 µs while
in burst mode
> Reduces production programming cost
through ultra-fast programming
> 5V Flash program/erase/read
> No external high voltage or charge
pump required
HCS12 CPU
> Flash granularity—512 byte Flash
erase/2 byte Flash program
> Virtual EEPROM implementation, Flash array
usable for EE extension
2 x SCI
> Four independently programmable
Flash arrays
256 KB Flash
> Can erase one array while executing code
from another
I2C
3 x SPI
> Flexible block protection and security
12 KB RAM
4 KB EEPROM
4 KB Integrated EEPROM
Vreg
5V to 2.5V
> Flexible protection scheme for protection
against accidental program or erase
> Can erase 4 bytes at a time and program
2 bytes at a time for calibration, security,
personality and diagnostic information
ATD0
10-bit, 8-ch.
ATD1
10-bit, 8-ch.
16-Key Wake-Up
IRQ Ports
> EEPROM can be programmed in 46 µs
Enhanced Capture Timer
16-bit, 8-ch.
2 x CAN
2.0 A/B
PWM
8-bit, 8 ch./16-bit, 4-ch.