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9P035YFLF-T PDF预览

9P035YFLF-T

更新时间: 2024-01-14 09:10:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 191K
描述
PLL Based Clock Driver, 9P Series, 6 True Output(s), 0 Inverted Output(s), PDSO8, 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-8

9P035YFLF-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.77系列:9P
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:10.2 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:8
实输出次数:6最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.04 ns座面最大高度:2 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mmBase Number Matches:1

9P035YFLF-T 数据手册

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DATASHEET  
ICS9P935  
DDR I/DDR II Phase Lock Loop Zero Delay Buffer  
Description  
Pin Configuration  
DDR I/DDR II Zero Delay Clock Buffer  
DDRC0 1  
DDRT0 2  
VDD2.5/1.8 3  
DDRT1 4  
28 GND  
27 DDRC5  
26 DDRT5  
25 VDD2.5/1.8  
24 GND  
23 DDRC4  
22 DDRT4  
21 VDD2.5/1.8  
20 SDATA  
19 SCLK  
Output Features  
Low skew, low jitter PLL clock driver  
Max frequency supported = 400MHz (DDRII 800)  
DDRC1 5  
I2C for functional and output control  
GND 6  
VDDA2.5/1.8 7  
GND 8  
CLK_INT 9  
CLK_INC 10  
VDD2.5/1.8 11  
DDRT2 12  
DDRC2 13  
GND 14  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
Programmable skew through SMBus  
Frequency defect control thorugh SMBus  
Individual output control programmable through SMBus  
18 FB_IN  
Key Specifications  
17 FB_OUT  
16 DDRT3  
15 DDRC3  
CYCLE - CYCLE jitter: <100ps  
OUTPUT - OUTPUT skew: <100ps  
DUTY CYCLE: 48% - 52%  
28-pin SSOP package  
28-SSOP/TSSOP  
Available in RoHS compliant packaging  
Operates @ 2.5V or 1.8V  
Funtional Block Diagram  
FB_OUT  
Control  
Logic  
SCLK  
DDRT0  
DDRC0  
SDATA  
DDRT1  
DDRC1  
DDRT2  
DDRC2  
DDRT3  
DDRC3  
FB_IN  
CLK_INT  
CLK_INC  
PLL  
DDRT4  
DDRC4  
DDRT5  
DDRC5  
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer  
ICS9P935  
REV H 12/1/08  
1

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