Datasheet > 9LPRS545BFLF

9LPRS545BFLF

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
17页	215K
描述
Microprocessor Circuit, PDSO48, 0.300 INCH, MO-118, SSOP-48

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9LPRS545BFLF 数据手册

Integrated

Circuit

Systems, Inc.

ICS9LPRS545

Datasheet

Test Clarification Table

Comments

FSLB/

FSLC/

TEST_SEL

HW PIN

TEST_MOD

TEST

REF/N or

HW PIN

ENTRY BIT

HI-Z

B9b4

B9b3

OUTPUT

NORMAL

HI-Z

<2.0V

>2.0V

Power-up w/ TEST_SEL = 1 to enter test mode

Cycle power to disable test mode

REF/N

FSLC./TEST_SEL -->3-level latched input

If power-up w/ V>2.0V then use TEST_SEL

If power-up w/ V<2.0V then use FSLC

FSLB/TEST_MODE -->low Vth input

TEST_MODE is a real time input

>2.0V

<2.0V

REF/N

HI-Z

If TEST_SEL HW pin is 0 during power-up,

test mode can be invoked through B9b3.

If test mode is invoked by B9b3, only B9b4

is used to select HI-Z or REF/N

<2.0V

REF/N

FSLB/TEST_Mode pin is not used.

Cycle power to disable test mode, one shot control

B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)

B9b4: 1= REF/N, Default = 0 (HI-Z)

1479A—07/28/09

1...11 12 131415 16 17

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