Datasheet > 9FGU0441_16

9FGU0441_16

更新时间： 2022-02-26 10:49:51

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
15页	202K
描述
4 O/P 1.5V PCIe Gen1-2-3 Clock Generator

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9FGU0441_16 数据手册

9FGU0441 DATASHEET

Pin Descriptions

Pin# Pin Name

Type

GND

Pin Description

GND for XTAL

GNDXTAL

XIN/CLKIN_25

Crystal input or Reference Clock input. Nominally 25MHz.

OUT

PWR

LATCHED

I/O

Crystal output.

Power supply for XTAL, nominal 1.5V

VDD for REF output. nominal 1.5V.

VDDXTAL1.5

VDDREF1.5

vSADR/REF1.5

Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin

GNDREF

GNDDIG

VDDDIG1.5

SCLK_3.3

SDATA_3.3

GND

PWR

Ground pin for the REF outputs.

Ground pin for digital circuitry

1.5V digital power (dirty power)

Clock pin of SMBus circuitry, 3.3V tolerant.

Data pin for SMBus circuitry, 3.3V tolerant.

Active low input for enabling DIF pair 0. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

I/O

vOE0#

DIF0

DIF0#

GND

OUT

GND

PWR

Differential true clock output

Differential Complementary clock output

Ground pin.

Power supply for outputs, nominally 1.5V.

Active low input for enabling DIF pair 1. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

VDDO1.5

vOE1#

DIF1

OUT

GND

PWR

OUT

Differential true clock output

Differential Complementary clock output

Ground pin for the PLL core.

1.5V power for the PLL core.

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 2. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

DIF1#

GNDA

VDDA1.5

DIF2

DIF2#

vOE2#

VDDO1.5

GND

DIF3

PWR

GND

OUT

Power supply for outputs, nominally 1.5V.

Ground pin.

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 3. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

DIF3#

vOE3#

GND

Ground pin.

Input notifies device to sample latched inputs and start up on first high assertion.

Low enters Power Down Mode, subsequent high assertions exit Power Down

Mode. This pin has internal pull-up resistor.

Latched select input to select spread spectrum amount at initial power up :

1 = -0.5% spread, M = -0.25%, 0 = Spread Off

^CKPWRGD_PD#

vSS_EN_tri

LATCHED IN

OCTOBER 18, 2016

4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS

1 234 5 6 7...15

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