9FGU0431 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Supply Voltage
SYMBOL
VDDxx
CONDITIONS
MIN
TYP
1.5
MAX
UNITS NOTES
V
Supply voltage for core, analog and single-ended
LVCMOS outputs
1.425
1.575
Ambient Operating
Temperature
Comercial range
0
25
25
70
85
°C
°C
V
TAMB
Industrial range
-40
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VIH
VIM
VIL
VIH
VIL
IIN
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
0.75 VDD
0.4 VDD
-0.3
VDD + 0.3
0.5 VDD 0.6 VDD
0.25 VDD
V
V
Single-ended outputs, except SMBus. IOH = -2mA VDD-0.45
Single-ended outputs, except SMBus. IOL = -2mA
V
0.45
5
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IN = 0 V; Inputs with internal pull-up resistors
IN = VDD; Inputs with internal pull-down resistors
XTAL, or X1 input
-5
-200
23
uA
Input Current
V
IINP
200
uA
V
Input Frequency
Pin Inductance
Fin
Lpin
25
27
7
MHz
nH
pF
pF
1
1
1
CIN
Logic Inputs, except DIF_IN
Output pin capacitance
1.5
5
Capacitance
COUT
6
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Triangular Modulation
Clk Stabilization
TSTAB
1.8
ms
1,2
SS Modulation Frequency
OE# Latency
fMOD
30
1
31.6
33
3
kHz
1
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
tLATOE#
clocks
1,3
Tdrive_PD#
tDRVPD
300
us
1,3
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
ns
ns
V
2
2
Trise
tR
Rise time of single-ended control inputs
5
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
0.6
3.3
0.4
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
2.1
V
4
SMBus Output Low Voltage VOLSMB
@ IPULLUP
@ VOL
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
4
mA
V
1.425
3.3
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
Maximum SMBus operating frequency
400
kHz
1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
6
OCTOBER 18, 2016