9FGU0431 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGU0431. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
-0.5
TYP
MAX
2
VDD+0.5V
Supply Voltage
Input Voltage
VDDxx
VIN
Applies to all VDD pins
V
V
1,2
1,3
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
3.3V
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
IDDAOP
CONDITIONS
MIN TYP MAX UNITS NOTES
VDDA, All outputs active @100MHz
6.2
9
mA
Operating Supply Current
All VDD, except VDDA, All outputs active
@100MHz
IDDOP
IDDAPD
IDDPD
20
27
mA
VDDA, DIF outputs off, REF output running
0.4
4.3
1
mA
mA
2
2
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
All VDD, except VDDA,
DIF outputs off, REF output running
6.5
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
IDDAPD
IDDPD
VDDA, all outputs off
0.4
0.4
1
1
mA
mA
All VDD, except VDDA and VDDIO, all outputs off
1 Guaranteed by design and characterization, not 100% tested in production.
2 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Duty Cycle
tDC
tsk3
Measured differentially, PLL Mode
Averaging on, VT = 50%
45
50
32
16
55
50
50
%
ps
ps
1,2
1
Skew, Output to Output
Jitter, Cycle to cycle
tjcyc-cyc
1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
OCTOBER 18, 2016
5
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR