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9FGP205AKLFT PDF预览

9FGP205AKLFT

更新时间: 2024-02-11 18:57:00
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
18页 257K
描述
Frequency Timing Generator for Peripherals

9FGP205AKLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:VFQFPN
包装说明:HVQCCN, LCC40,.24SQ,20针数:40
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:4.51
Samacsys Description:VFQFP-N 6.0 X 6.0 X 0.9 MM - NO LEADJESD-30 代码:S-PQCC-N40
JESD-609代码:e3长度:6 mm
湿度敏感等级:3端子数量:40
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:400 MHz封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC40,.24SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:1 mm子类别:Clock Generators
最大压摆率:225 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:6 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC

9FGP205AKLFT 数据手册

 浏览型号9FGP205AKLFT的Datasheet PDF文件第12页浏览型号9FGP205AKLFT的Datasheet PDF文件第13页浏览型号9FGP205AKLFT的Datasheet PDF文件第14页浏览型号9FGP205AKLFT的Datasheet PDF文件第15页浏览型号9FGP205AKLFT的Datasheet PDF文件第16页浏览型号9FGP205AKLFT的Datasheet PDF文件第17页 
9FGP205  
Advance Information  
Frequency Timing Generator for Peripherals  
Revision History  
Rev. Issue Date  
Who  
Description  
Page #  
0.1  
4/13/2009  
RDW  
Initial Release  
-
1. Changed name of Pin 40 to CKPWRGD_WOL_STOP# to update  
description. No change in functionality.  
2. Added control bits to Byte 3, 4, and 5 to select WOL_STOP#  
functionality for the 25M REF outputs and the 50M RMII outputs. Note  
default settings.  
0.2  
4/30/2010  
RDW  
3. Updated Table 1 (combined with Table 2)  
4. Changed Table 2 to reflect WOL_STOP function for pins 16, 29, 32,  
33.  
5. Added WOL_STOP entry for power down current.  
6. Updated/corrected block diagram by removing OE_RMII pins.  
0.3  
0.4  
5/3/2010  
RDW  
RDW  
5
1. Corrected error in Truth Table 2, added separate column for Pin 22.  
1. CPU and DOT 96 default power down mode changed from driven to  
Hi-Z to support WOL_STOP# mode. Termination circuit will give  
Low/Low on those outputs in Power Down. Byte 2, but 7 and 6 default  
changed to 1.  
13, 14  
5/14/2010  
2. Corrected byte 7 to be Read Only.  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
800-345-7015  
408-284-6578  
408-284-8200  
pcclockhelp@idt.com  
Fax: 408-284-2775  
Corporate Headquarters  
Asia Pacific and Japan  
Europe  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
IDT Singapore Pte. Ltd.  
1 Kallang Sector #07-01/06  
KolamAyer Industrial Park  
Singapore 349276  
IDT Europe Limited  
321 Kingston Road  
Leatherhead, Surrey  
KT22 7TU  
United States  
800 345 7015  
+408 284 8200 (outside U.S.)  
Phone: 65-6-744-3356  
Fax: 65-6-744-1764  
England  
Phone: 44-1372-363339  
Fax: 44-1372-378851  
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks  
of Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks  
a
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
18  

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