Datasheet > 9FGP204

9FGP204

更新时间： 2022-09-27 10:18:21

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	171K
描述
Frequency Timing Generator for Peripherals

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9FGP204 数据手册

9FGP204

Frequency Timing Generator for Peripherals

General Description

The 9FGP204 is a peripheral clock for Intel Servers. It is driven with a 25MHz crystal and generates a variety of clocks,

including 125MHz RGMII. An SMBus interface allows full control of the device.

Block Diagram

25MHz(1:0)

X1_25

XTAL

X2_25

CPU PLL

CPUCLK

(SPREAD

CAPABLE)

DOT PLL

(SPREAD

CAPABLE)

DOT96SS

VttPwr_GD/PD#

OE_CPU

OE_96

33.33MHz

RGMII(1:0)

RMII(5:0)

CONTROL

LOGIC

FIXED

PLL

DIVIDERS

SMBADR

SMBDAT

SMBCLK

32.768KHz

Power Supply Pins

Pin Number

Description

VDD

GND

CPUCLK output and PLL

DOT96SS output and PLL

26,31

27,30

125 MHz RGMII outputs and PLL

50 MHz RMII outputs

33.33MHz output

32.768KHz output

XTAL, REF outputs

Note: All VDD should be connected to a common power rail with proper

filtering and decoupling. Pins 2, 9 and 34 should be treated as analog pins for

decoupling purposes.

IDT^®Frequency Timing Generator for Peripherals

1604B—08/29/11

1 234 5 6 7...18

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