Datasheet > 9FGP204BKLF

9FGP204BKLF

更新时间： 2022-09-27 10:18:21

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	171K
描述
Frequency Timing Generator for Peripherals

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9FGP204BKLF 数据手册

DATASHEET

Frequency Timing Generator for Peripherals

9FGP204

Pin Configuration

Recommended Application:

Peripheral Clock for Intel Server

Output Features:

•

1 - 0.7V current-mode differential CPU pair

6 - 50MHz RMII outputs

2 - 125MHz RGMII outputs

1 - DOT 96MHz output

1 - 33.33MHz output

1 - 32.768KHz output

40 39 38 37 36 35 34 33 32 31

GND

VDD96

DOT96SST

DOT96SSC

OE_96

OE_CPU

CPUCLKT0

CPUCLKC0

VDDCPU

GNDCPU

GNDRMII

RMII2

RMII3

GNDRMII

VDDRMII

RMII4

RMII5

VDD33

33.33MHZ/**SMBADR

GND33

2 - 25MHz REF outputs

9FGP204

Key Specifications:

•

Exact synthesis on CPU, RGMII, RMII & 33.33MHz

clocks

11 12 13 14 15 16 17 18 19 20

•

+/- 100ppm frequency accuracy on other clocks

Features/Benefits:

40-MLF

* Internal Pull-Up Resistor

** Internal Pull-Dow n Resistor

•

Selectable SMBus Address - D0/D1 or C0/C1

Spread Spectrum capability on CPU and DOT 96MHz

clocks

•

SMBus Control:

- M/N and spread programming on CPU and DOT

96MHz clocks via SMBus

- Differential outputs can be disabled via pins or SMBus

Functionality

CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS

33.33

MHz

RMII

MHz

RGMII

MHz

32.768

KHz

MHz

266.67

133.33

200.00

166.67

333.33

100.00

400.00

Reserved

MHz

Byte0 Bit2 Byte0 Bit1 Byte0 Bit0

96.00

33.33

50.00

125.00

25.00

32.768

Power up default is highlighted.

SMBus Address Selection

SMBADR

*SMBADR = 0 SMBADR = 1

D0/D1

C0/C1

* Default value

IDT^®Frequency Timing Generator for Peripherals

1604B—08/29/11

12 3 4 5 6 7...18

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