Datasheet > 9FGP204BKLF

9FGP204BKLF

更新时间： 2022-09-27 10:18:21

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	171K
描述
Frequency Timing Generator for Peripherals

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9FGP204BKLF 数据手册

9FGP204

Frequency Timing Generator for Peripherals

Truth Table 1: VttPwr_GD/PD# and OE_96

VttPwr_GD/PD#

OE_96

Pin 5

Clocks

Pin 40

All clocks are powered down

All clocks are enabled except DOT96SS

*All clocks are enabled including DOT96SS

*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)

Truth Table 2: VttPwr_GD/PD# and OE_CPU

VttPwr_GD/PD#

OE_CPU

Pin 6

Clocks

Pin 40

All clocks are powered down

All clocks are enabled except CPUCLK

*All clocks are enabled including CPUCLK

*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)

Table 1: CPU Spread and Frequency Selection

CPU

SS_EN

CPU

MHz

Down

Spread %

FS2

Byte 0

FS1

Byte 0

FS0

Byte 0

Bit 3

Bit 2

Bit 1

Bit 0

266.67

133.33

200.00

166.67

333.33

100.00

400.00

200.00

266.67

133.33

200.00

166.67

333.33

100.00

400.00

200.00

0.5%

IDT^®Frequency Timing Generator for Peripherals

1604B—08/29/11

1 2 3 456 7 8...18

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