9FGP204
Frequency Timing Generator for Peripherals
Pin Description
PIN
PIN #
PIN NAME
DESCRIPTION
TYPE
PWR
PWR
1
2
GND
Ground pin.
VDD96
Power pin for the DOT96 clocks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are
current mode outputs. External resistors are required for voltage bias.
Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
These are current mode outputs. External resistors are required for voltage bias.
Active high input for enabling 96Hz outputs.
1 = enable output(s), 0 =disable output(s)
Active high input for enabling CPU DIFF pairs.
1 = enable output(s), 0 =disable output(s)
True clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
3
4
5
6
7
DOT96SST
OUT
OUT
IN
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
IN
OUT
OUT
Complementary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
8
9
CPUCLKC0
VDDCPU
PWR
PWR
10 GNDCPU
Ground pin for the CPU outputs
This pin establishes the reference for the differential current-mode output pairs. It requires a
fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential
impedance. Other impedances require different values. See data sheet.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
11 IREF
OUT
12 VDD32K
13 32.768KHz
14 GND32K
15 VDDREF
16 25MHz_0
17 25MHZ_1
18 GNDREF
19 X1_25
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
Ground pin for the REF outputs.
Crystal input, Nominally 25.00MHz.
20 X2_25
21 GND33
OUT
PWR
Crystal output.
Ground pin for the 33.33MHz outputs
22 33.33MHZ/**SMBADR
I/O
33.33MHz clock output / SMBus address select bit.
23 VDD33
24 RMII5
25 RMII4
26 VDDRMII
27 GNDRMII
28 RMII3
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
Power pin for the 33.33MHz outputs, nominal 3.3V
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the RMII outputs
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
Ground pin for the RMII outputs
3.3V power pin for the RMII clocks.
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RGMII clocks and PLL
Ground pin for the RGMII outputs
3.3V 125MHz RGMII clock output
29 RMII2
30 GNDRMII
31 VDDRMII
32 RMII1
33 RMII0
34 VDDRGMII
35 GNDRGMII
36 RGMII1
37 RGMII0
38 SMBCLK
39 SMBDAT
3.3V 125MHz RGMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid
and are ready to be sampled. This is an active high input. / Asynchronous active low input pin
used to power down the device into a low power state.
I/O
40 VttPwr_GD/PD#
IN
IDT® Frequency Timing Generator for Peripherals
1604B—08/29/11
2
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