Datasheet > 9FGP204

9FGP204

更新时间： 2022-09-27 10:18:21

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	171K
描述
Frequency Timing Generator for Peripherals

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9FGP204 数据手册

9FGP204

Frequency Timing Generator for Peripherals

Absolute Maximum Ratings

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS Notes

GND -

0.5

GND +

4.5

3.3V

3.3V Supply Voltage

VDDxxx

Maximum difference across all

VDD pins

VDDdelta

0.5

Storage Temperature

-65

150

^°C

°C

Ambient Operating Temp

Junction Temperature

Tambient

125

Input ESD protection HBM

ESD prot

2000

¹Guaranteed by design and characterization, not 100% tested in production.

Electrical Characteristics - Input/Supply/Common Output Parameters

PARAMETER

Input High Voltage

Input Low Voltage

Input High Current

SYMBOL

CONDITIONS*

3.3 V +/-5%

V_IN= V_DD

MIN

TYP

MAX

V_DD+ 0.3

0.8

UNITS Notes

V_IH

V_IL

I_IH

V_SS- 0.3

-5

V_IN= 0 V; Inputs with no pull-up

resistors

I_IL1

-5

Input Low Current

V_IN= 0 V; Inputs with pull-up

resistors

I_IL2

-200

Low Threshold Input-

High Voltage

Low Threshold Input-

Low Voltage

V_{IH_FS}

3.3 V +/-5%

0.7

V_DD+ 0.3

0.35

V_{IL_FS}

V_SS- 0.3

Operating Current

I_DD3.3OP

all outputs driven, CPU@100M

all diff pairs driven

225

MHz

204

Powerdown Current

I_DD3.3PD

all differential pairs tri-stated

V_DD= 3.3 V

Input Frequency

Pin Inductance

F_i

25.00000

L_pin

C_IN

Logic Inputs

Output pin capacitance

X1 & X2 pins

Input Capacitance

C_OUT

C_INX

From VDD Power-Up or de-

assertion of PD to 1st clock

Triangular Modulation

Clk Stabilization

Modulation Frequency

Tdrive_PD

T_STAB

0.5

2.5

kHz

CPU output enable after

PD de-assertion

PD fall time of

260

300

Tfall_PD

Trise_PD

PD rise time of

SMBus Voltage

V_DD

V_OL

2.7

5.5

0.4

Low-level Output Voltage

Current sinking at

@ I_PULLUP

I_PULLUP

V_OL= 0.4 V

SCLK/SDATA

Clock/Data Rise Time

SCLK/SDATA

(Max VIL - 0.15) to

(Min VIH + 0.15)

(Min VIH + 0.15) to

(Max VIL - 0.15)

T_RI2C

T_FI2C

1000

300

Clock/Data Fall Time

*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

¹Guaranteed by design and characterization, not 100% tested in production.

²Input frequency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs.

IDT^®Frequency Timing Generator for Peripherals

1604B—08/29/11

1...4 5 678 9 10...18

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