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9EX21801AKLF PDF预览

9EX21801AKLF

更新时间: 2024-02-18 16:16:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器复用器逻辑集成电路PC
页数 文件大小 规格书
14页 162K
描述
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

9EX21801AKLF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:ROHS COMPLIANT, PLASTIC, MLF-72针数:72
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N系列:9EX
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-N72
JESD-609代码:e3长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:72实输出次数:18
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC72,.39SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

9EX21801AKLF 数据手册

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ICS9EX21801A  
Datasheet  
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux  
Pin Description  
PIN #  
PIN NAME  
PIN TYPE  
DESCRIPTION  
1
VDD  
PWR  
Power supply, nominal 3.3V  
Active low input for enabling DIF pair 10.  
1 = tri-state outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential complement clock output  
Active low input for enabling DIF pair 11.  
1 = tri-state outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential complement clock output  
Active low input for enabling DIF pair 12.  
1 = tri-state outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential complement clock output  
Ground pin.  
2
OE10#  
IN  
3
4
DIF_10  
DIF_10#  
OUT  
OUT  
5
OE11#  
IN  
6
7
DIF_11  
DIF_11#  
OUT  
OUT  
8
OE12#  
IN  
9
DIF_12  
DIF_12#  
GND  
VDD  
DIF_13  
DIF_13#  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
10  
11  
12  
13  
14  
Power supply, nominal 3.3V  
0.7V differential true clock output  
0.7V differential complement clock output  
Active low input for enabling DIF pair 13.  
1 = tri-state outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential complement clock output  
Active low input for enabling DIF pair 14.  
1 = tri-state outputs, 0 = enable outputs  
0.7V differential true clock output  
15  
OE13#  
IN  
16  
17  
DIF_14  
DIF_14#  
OUT  
OUT  
18  
OE14#  
IN  
19  
20  
21  
DIF_15  
DIF_15#  
VDD  
OUT  
OUT  
PWR  
0.7V differential complement clock output  
Power supply, nominal 3.3V  
Active low input for enabling DIF pairs 15, 16 and 17  
1 = tri-state outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential complement clock output  
0.7V differential true clock output  
22  
OE15_17#  
IN  
23  
24  
25  
26  
DIF_16  
DIF_16#  
DIF_17  
DIF_17#  
OUT  
OUT  
OUT  
OUT  
0.7V differential complement clock output  
This pin establishes the reference current for the differential current-mode output pairs. This pin  
requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475  
ohms is the standard value.  
27  
IREF  
OUT  
28  
29  
30  
31  
32  
33  
34  
35  
GNDA  
VDDA  
PWR  
PWR  
IN  
IN  
PWR  
IN  
Ground pin for the PLL core.  
3.3V power for the PLL core.  
True Input for differential reference clock.  
Complement Input for differential reference clock.  
Ground pin.  
True Input for differential reference clock.  
Complement Input for differential reference clock.  
Power supply, nominal 3.3V  
CLKA_IN  
CLKA_IN#  
GND  
CLKB_IN  
CLKB_IN#  
VDD  
IN  
PWR  
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.  
1 = tri-state outputs, 0 = enable outputs  
36  
OE_01234#  
IN  
IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux  
1463B — 01/20/10  
3

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