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9EX21801AKLF PDF预览

9EX21801AKLF

更新时间: 2024-01-31 09:02:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器复用器逻辑集成电路PC
页数 文件大小 规格书
14页 162K
描述
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

9EX21801AKLF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:ROHS COMPLIANT, PLASTIC, MLF-72针数:72
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N系列:9EX
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-N72
JESD-609代码:e3长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:72实输出次数:18
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC72,.39SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

9EX21801AKLF 数据手册

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ICS9EX21801A  
Datasheet  
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux  
Revision History  
Rev.  
Issue Date Description  
Page #  
0.1  
4/29/2008 Initial Release  
-
1. SMBus Bytes 11-16 are now reserved  
2. SMBus References to 1:1 operating set point register are removed.  
5/1/2008 3. Updated readback registers to match new control pins  
3. Added QPI phase noise spec  
0.2  
Various  
4. Significant changes to pinout to improve performance  
1. Updated/Corrected SMBus, filled in empty bytes  
2. Updated Frequency/Functionality Table  
3. Added SMBus Address decoding table and graph  
4. Corrected Power hook up table.  
6/3/2008 Added revision designator to orderng information  
1. Updated front page text  
0.3  
0.4  
5/30/2008  
Various  
12  
2. Updated Functionality foot notes on Page 2.  
3. Deleted duplicate table on page 6.  
4. Corrected DIF 0.7V Current Mode electrical characterisitcs - removed  
skew spec.  
1,2,6,7,8,  
10  
0.5  
12/8/2008  
5. Updated skew and Differential Parameters Table to reflect char data,  
added PLL BW and jitterpeaking data to this table.  
6. Updated Phase Jitter Table - removed FBD specs and added HiBW and  
Low BW sections  
7. Added SMBus Addressing Table after page 9  
1. Updated PLL mode input frequency range  
2. Noted that Modulation frequency is the Allowable Spread Modulation  
Frequency. Added foonote 3.  
3. Corrected PCIe Gen1 Max phase jitter spec to be 86 ps instead of  
108ps. 86ps is the derated limit when using ~160K cycles to calculate the  
value. Released to final - Rev A.  
A
B
12/17/2008  
5,8  
4
1/20/2010 1. Corrected Pin Description for Pin 62. 0 = 133M, 1 = 100M.  
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Europe  
Integrated Device Technology, Inc.  
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Integrated Device Technology  
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Reg. No. 199707558G  
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Singapore 238877  
IDT Europe, Limited  
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United Kingdom KT22 7DE  
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TM  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks  
or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
14  

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