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9DBU0541AKLFT PDF预览

9DBU0541AKLFT

更新时间: 2024-02-16 18:52:50
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
17页 218K
描述
5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms

9DBU0541AKLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
系列:9DBU输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1 mm
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5 mmBase Number Matches:1

9DBU0541AKLFT 数据手册

 浏览型号9DBU0541AKLFT的Datasheet PDF文件第2页浏览型号9DBU0541AKLFT的Datasheet PDF文件第3页浏览型号9DBU0541AKLFT的Datasheet PDF文件第4页浏览型号9DBU0541AKLFT的Datasheet PDF文件第5页浏览型号9DBU0541AKLFT的Datasheet PDF文件第6页浏览型号9DBU0541AKLFT的Datasheet PDF文件第7页 
5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer  
with Zo=100ohms  
9DBU0541  
DATASHEET  
Description  
Features/Benefits  
The 9DBU0541 is a member of IDT's 1.5V Ultra-Low-Power  
(ULP) PCIe family. It has integrated terminations for direct  
connection to 100transmission lines. The device has 5  
output enables for clock management, and 3 selectable  
SMBus addresses.  
Integrated terminations; save 20 resistors compared to  
standard HCSL outputs  
35mW typical power consumption; eliminates thermal  
concerns  
Spread Spectrum (SS) compatible; allows SS for EMI  
reduction  
Recommended Application  
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)  
OE# pins; support DIF power management  
HCSL-compatible differential input; can be driven by  
common clock sources  
Output Features  
SMBus-selectable features; optimize signal integrity to  
application  
5 1–167MHz Low-Power (LP) HCSL DIF pairs with  
Z =100  
O
slew rate for each output  
Key Specifications  
DIF additive cycle-to-cycle jitter < 5ps  
DIF output-to-output skew < 60ps  
DIF additive phase jitter is < 300fs rms for PCIe Gen3  
DIF additive phase jitter < 350fs rms for SGMII  
differential output amplitude  
Device contains default configuration; SMBus interface not  
required for device control  
3.3V tolerant SMBus interface works with legacy controllers  
Selectable SMBus addresses; multiple devices can easily  
share an SMBus segment  
5 × 5 mm 32-VFQFPN; minimal board space  
Block Diagram  
vOE(4:0)#  
5
CLK_IN  
DIF4  
DIF3  
DIF2  
DIF1  
DIF0  
CLK_IN#  
vSADR  
^CKPWRGD_PD#  
SDATA_3.3  
CONTROL  
LOGIC  
SCLK_3.3  
9DBU0541 MARCH 9, 2017  
1
©2017 Integrated Device Technology, Inc.  

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