Datasheet > 9DBU0941AKLFT

9DBU0941AKLFT

更新时间： 2024-02-17 12:59:34

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
17页	218K
描述
9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms

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数据手册

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9DBU0941AKLFT 数据手册

9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer

with Zo=100ohms

9DBU0941

DATASHEET

Description

Features/Benefits

The 9DBU0941 is a member of IDT's 1.5V Ultra-Low-Power

(ULP) PCIe family. It has integrated terminations for direct

connection to 100 transmission lines. The device has 9

output enables for clock management, and 3 selectable

SMBus addresses.

• Direct connection to 100 transmission lines; save 36

resistors compared to standard HCSL outputs

• 47mW typical power consumption; eliminates thermal

concerns

• Outputs can optionally be supplied from any voltage

between 1.05 and 1.5V; maximum power savings

Recommended Application

1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)

• Spread Spectrum (SS) compatible; allows SS for EMI

reduction

• OE# pins for each output; support DIF power management

• HCSL-compatible differential input; can be driven by

common clock sources

Output Features

• 9 1–167MHz Low-Power (LP) HCSL DIF pairs with

ZO=100

• SMBus-selectable features; optimize signal integrity to

application

Key Specifications

• DIF additive cycle-to-cycle jitter < 5ps

• DIF output-to-output skew < 60ps

• DIF additive phase jitter is < 300fs rms for PCIe Gen3

• DIF additive phase jitter < 350s rms for SGMII

• slew rate for each output

• differential output amplitude

• Device contains default configuration; SMBus interface not

required for device operation

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

• 3.3V tolerant SMBus interface works with legacy controllers

• 6 × 6 mm 48-VFQFPN; minimal board space

Block Diagram

vOE(8:0)#

DIF8

DIF7

DIF6

DIF5

DIF4

DIF3

DIF2

DIF1

DIF0

CLK_IN

CLK_IN#

vSADR

^CKPWRGD_PD#

SDATA_3.3

CONTROL

LOGIC

SCLK_3.3

9DBU0941 MARCH 9, 2017

12 3 4 5 6 7...17

中文翻译

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