9DBV05x1/9DBV07x1/
9DBV09x1
5 to 9-Output 1.8V Low-Power
Buffers for PCIe Gen1–5
Datasheet
Description
Features
▪ 5–9 Low-Power HCSL (LP-HCSL) outputs
The 9DBV05x1/9DBV07x1/9DBV09x1 fanout buffers are
low-power, high-performance fanout buffers in Renesas' Full
Featured PCIe family. The buffers have 5, 7 or 9 outputs with each
output having an OE# to support the PCIe CLKREQ# function.
The devices have 3 selectable SMBus addresses.
• 100Ω outputs eliminate 4 resistors per output pair
(9DBVxx41)
• 33Ω outputs eliminate 2 resistors per output pair allowing
use in both 85Ω and 100Ω systems (9DBVxx31)
▪ Easy AC-coupling to other logic families, see application note
AN-891
PCIe Clocking Architectures
▪ Common Clocked (CC)
▪ Spread spectrum compatible
▪ Independent Reference (IR) with and without spread spectrum
(SRIS, SRNS)
▪ OE# pins support PCIe CLKREQ# function
▪ 3 selectable SMBus addresses
▪ 3.3V tolerant SMBus interface
Typical Applications
▪ Servers/High-performance Computing
▪ nVME Storage
▪ SMBus-selectable features allow optimization to customer
requirements:
• Individual slew rate control for each output
• Differential output amplitude
• Device contains default configuration; SMBus interface not
required for device operation
▪ Networking
▪ Accelerators
▪ Industrial Control
▪ -40°C to +85°C operating temperature range
Key Specifications
▪ PCIe Gen5 CC additive phase jitter <40fs RMS
▪ Packages: See Ordering Information for more details
▪ 12kHz–20MHz additive phase jitter = 165fs RMS at 156.25MHz
(typical)
▪ Output-to-output skew < 50ps
▪ Power consumption as low as 41mW (typical)
▪ 1MHz to 200MHz operating frequency
Block Diagram
7 and 9 output parts
only
VDDDIG1.8
VDDR1.8
VDDIO
CLK_IN#
CLK_IN
DIFn#
DIFn
vSADR_tri
5, 7 or 9
outputs
SMBus
Engine Configuration
Factory
SMBCLK
SMBDAT
DIF0#
DIF0
^CKPWRGD_PD#
vOE[n:0]#
n+1
Control Logic
Resistors are integrated on
9DBVxx4x
GNDR
EPAD/GND
GNDDIG
©2017–2023 Renesas Electronics Corporation
1
February 6, 2023