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9DBU0541AKLFT PDF预览

9DBU0541AKLFT

更新时间: 2024-01-07 19:20:31
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
17页 218K
描述
5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms

9DBU0541AKLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
系列:9DBU输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1 mm
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5 mmBase Number Matches:1

9DBU0541AKLFT 数据手册

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9DBU0541 DATASHEET  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9DBU0541. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the  
recommended operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
-0.5  
-0.5  
TYP  
MAX  
2
VDD+0.5  
Supply Voltage  
Input Voltage  
VDDx  
VIN  
Applies to all VDD pins  
V
V
1,2  
1,  
Input High Voltage, SMBus  
VIHSMB  
Ts  
Tj  
SMBus clock and data pins  
3.3  
150  
125  
V
1
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD Protection  
-65  
°C  
°C  
V
ESD prot  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 2.0V.  
Electrical Characteristics–Clock Input Parameters  
TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
mV  
Input Common Mode  
Voltage - DIF_IN  
VCOM  
Common mode input voltage  
200  
725  
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
VIN = VDD , VIN = GND  
300  
0.4  
-5  
1450  
8
5
mV  
V/ns  
uA  
Input Duty Cycle  
dtin  
Measurement from differential waveform  
45  
50  
55  
%
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential measurement  
0
150  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through +/-75mV window centered around differential zero.  
MARCH 9, 2017  
5
5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS  

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