ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Pin Decription When OE_INV = 0
PIN #
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
PIN TYPE
PWR
IN
DESCRIPTION
1
2
3
4
5
6
7
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
IN
PWR
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
8
OE_1
IN
9
10
11
DIF_2
DIF_2#
VDD
OUT
OUT
PWR
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
12
BYPASS#/PLL
IN
13
14
SCLK
SDATA
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal osc. (if any) are
stopped.
15
PD#
IN
16
17
DIF_STOP#
HIGH_BW#
IN
IN
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
18
19
20
VDD
DIF_5#
DIF_5
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
21
OE_6
IN
22
23
24
DIF_6#
DIF_6
VDD
OUT
OUT
PWR
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
25
OE_INV
IN
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
3.3V power for the PLL core.
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV L 10/07/09
3