9DB403DGLFT

更新时间： 2024-01-16 01:15:04

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	278K
描述
Four Output Differential Buffer for PCIe Gen 1 and Gen 2

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9DB403DGLFT 数据手册

ICS9DB403D

Four Output Differential Buffer for PCIe for Gen 1 and Gen 2

Pin Decription When OE_INV = 1

PIN #

PIN NAME

VDD

SRC_IN

SRC_IN#

GND

VDD

DIF_1

DIF_1#

PIN TYPE

PWR

DESCRIPTION

Power supply, nominal 3.3V

0.7 V Differential SRC TRUE input

0.7 V Differential SRC COMPLEMENTARY input

Ground pin.

Power supply, nominal 3.3V

PWR

OUT

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 1.

1 = tri-state outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Power supply, nominal 3.3V

OE1#

DIF_2

DIF_2#

VDD

OUT

PWR

Input to select Bypass(fan-out) or PLL (ZDB) mode

0 = Bypass mode, 1= PLL mode

BYPASS#/PLL

SCLK

SDATA

I/O

Clock pin of SMBus circuitry, 5V tolerant.

Data pin for SMBus circuitry, 3.3V tolerant.

Asynchronous active high input pin used to power down the device.

The internal clocks are disabled and the VCO is stopped.

Active High input to stop differential output clocks.

3.3V input for selecting PLL Band Width

0 = High, 1= Low

DIF_STOP

HIGH_BW#

VDD

DIF_5#

DIF_5

PWR

OUT

Power supply, nominal 3.3V

0.7V differential Complementary clock output

0.7V differential true clock output

Active low input for enabling DIF pair 6.

1 = tri-state outputs, 0 = enable outputs

0.7V differential Complementary clock output

0.7V differential true clock output

OE6#

DIF_6#

DIF_6

VDD

OUT

PWR

Power supply, nominal 3.3V

This latched input selects the polarity of the OE pins.

0 = OE pins active high, 1 = OE pins active low (OE#)

This pin establishes the reference current for the differential current-

mode output pairs. This pin requires a fixed precision resistor tied to

ground in order to establish the appropriate current. 475 ohms is the

standard value.

OE_INV

IREF

OUT

GNDA

VDDA

PWR

Ground pin for the PLL core.

3.3V power for the PLL core.

IDT^TM/ICS^TMFour Output Differential Buffer for PCIe Gen 1 and Gen 2

ICS9DB403D

REV L 10/07/09

1 2 345 6 7...19

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