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9DB233

更新时间： 2024-02-23 17:47:18
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
14页 197K
描述
Two Output Differential Buffer for PCIe Gen3

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9DB233 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：3.94
Samacsys Description：TSSOP 4.4 MM 0.65MM PITCH系列：9DB
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：6.5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：20实输出次数：2
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm

9DB233 数据手册

 浏览型号9DB233的Datasheet PDF文件第2页浏览型号9DB233的Datasheet PDF文件第3页浏览型号9DB233的Datasheet PDF文件第4页浏览型号9DB233的Datasheet PDF文件第6页浏览型号9DB233的Datasheet PDF文件第7页浏览型号9DB233的Datasheet PDF文件第8页 
9DB233  
Two Output Differential Buffer for PCIe Gen3  
Datasheet  
Electrical Characteristics - Clock Input Parameters  
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
VIHDIF  
CONDITIONS  
MIN  
600  
TYP  
800  
MAX  
1150  
UNITS NOTES  
Differential inputs  
(single-ended measurement)  
Differential inputs  
Input High Voltage - DIF_IN  
mV  
mV  
mV  
1
1
1
Input Low Voltage - DIF_IN  
VILDIF  
VCOM  
VSS - 300  
300  
0
300  
(single-ended measurement)  
Input Common Mode  
Voltage - DIF_IN  
Common Mode Input Voltage  
1000  
Input Amplitude - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
VSWING  
dv/dt  
IIN  
Peak to Peak value  
Measured differentially  
300  
0.4  
-5  
1450  
8
mV  
V/ns  
uA  
1
1,2  
1
VIN = VDD , VIN = GND  
5
Input Duty Cycle  
dtin  
Measurement from differential wavefrom  
Differential Measurement  
45  
0
55  
125  
%
1
Input Jitter - Cycle to Cycle  
JDIFIn  
ps  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs  
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX UNITS NOTES  
Slew rate  
Slew rate matching  
Trf  
∆Trf  
Scope averaging on  
Slew rate matching, Scope averaging on  
0.6  
2.5  
9.5  
4
20  
V/ns 1, 2, 3  
%
1, 2, 4  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope averaging  
on)  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
740  
8
850  
1
mV  
-150  
150  
1
Measurement on single ended signal using absolute  
value. (Scope averaging off)  
Scope averaging off  
Max Voltage  
Min Voltage  
Vswing  
Vmax  
Vmin  
Vswing  
760  
-3  
1150  
1
mV  
-300  
300  
250  
1
1506  
378  
54  
mV  
mV  
mV  
1, 2  
1, 5  
1, 6  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vcross_abs  
∆-Vcross  
Scope averaging off  
Scope averaging off  
550  
140  
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH  
=
6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the  
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.  
Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)  
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.  
Electrical Characteristics - Current Consumption  
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
IDD3.3OP  
CONDITIONS  
MIN  
TYP  
70  
MAX  
UNITS NOTES  
Operating Supply Current  
All outputs active @100MHz, CL = Full load;  
All diff pairs driven  
All differential pairs tri-stated  
mA  
mA  
mA  
1
80  
IDD3.3PD  
IDD3.3PDZ  
N/A  
N/A  
1
1
Powerdown Current  
1Guaranteed by design and characterization, not 100% tested in production.  
IDT® Two Output Differential Buffer for PCIe Gen3  
1667C—04/20/11  
5
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