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9DB233 PDF预览

9DB233

更新时间: 2024-01-13 23:49:30
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
14页 197K
描述
Two Output Differential Buffer for PCIe Gen3

9DB233 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:3.94
Samacsys Description:TSSOP 4.4 MM 0.65MM PITCH系列:9DB
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:20实输出次数:2
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm

9DB233 数据手册

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9DB233  
Two Output Differential Buffer for PCIe Gen3  
Datasheet  
Pin Description  
PIN # PIN NAME PIN TYPE  
DESCRIPTION  
3.3V input for selecting PLL Band Width  
1
PLL_BW  
SRC_IN  
IN  
IN  
0 = low, 1= high  
2
3
0.7 V Differential SRC TRUE input  
0.7 V Differential SRC COMPLEMENTARY input  
SRC_IN# IN  
Active low input for enabling DIF pair 0. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
4
vOE0#  
IN  
5
6
7
8
9
VDD  
PWR  
PWR  
OUT  
OUT  
PWR  
Power supply, nominal 3.3V  
GND  
Ground pin.  
DIF_0  
DIF_0#  
VDD  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply, nominal 3.3V  
10 SMBDAT I/O  
11 SMBCLK IN  
Data pin of SMBUS circuitry, 5V tolerant  
Clock pin of SMBUS circuitry, 5V tolerant  
Power supply, nominal 3.3V  
12 VDD  
13 DIF_1#  
14 DIF_1  
15 GND  
16 VDD  
PWR  
OUT  
OUT  
PWR  
PWR  
0.7V differential Complementary clock output  
0.7V differential true clock output  
Ground pin.  
Power supply, nominal 3.3V  
Active low input for enabling DIF pair 1. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
17 vOE1#  
IN  
This pin establishes the reference for the differential current-mode output pairs. It  
requires a fixed precision resistor to ground. 475ohm is the standard value for  
100ohm differential impedance. Other impedances require different values. See  
data sheet.  
18 IREF  
OUT  
19 GNDA  
20 VDDA  
PWR  
PWR  
Ground pin for the PLL core.  
3.3V power for the PLL core.  
Note:  
Pins preceeded by ' v ' have internal 120K ohm pull down resistors  
IDT® Two Output Differential Buffer for PCIe Gen3  
1667C—04/20/11  
3

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