Datasheet > 9DB206LLFT

9DB206LLFT

更新时间： 2024-02-14 23:59:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	292K
描述
Clock Driver

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9DB206LLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

9DB206LLFT 数据手册

ICS9DB206

Integrated

Circuit

Systems, Inc.

PCI EXPRESS

™

JITTER

ATTENUATOR

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise.The ICS9DB206 provides separate

power supplies to isolate any high switching noise from the out-

puts to the internal PLL.V_DDandV_DDAshould be individually con-

nected to the power supply plane through vias, and bypass ca-

pacitors should be used for each pin.To achieve optimum jitter

performance, power supply isolation is required. Figure 1 illus-

trates how a 24Ω resistor along with a 10µF and a .01µF by-

pass capacitor should be connected to eachV_DDApin.

3.3V

V_DD

.01µF

24Ω

V_DDA

.01µF

10µF

FIGURE 1. POWER SUPPLY FILTERING

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in

single ended levels. The reference voltage V_REF = V_DD/2 is the center of the input voltage swing. For example, if the input

generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andV_DD= 3.3V, V_REF should be 1.25V

should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.

VDD

Single Ended Clock Input

CLK

V_REF

nCLK

0.1u

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

9DB206CL

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 29, 2004

1...4 5 678 9 10...13

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