Datasheet > 9DB233

9DB233

更新时间： 2023-12-20 18:45:51

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
18页	370K
描述
2-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

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9DB233 数据手册

DATASHEET

TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

9DB233

Description

Features/Benefits

The 9DB233 zero-delay buffer supports PCIe Gen3

requirements, while being backwards compatible to PCIe

Gen2 and Gen1. The 9DB233 is driven by a differential

SRC output pair from an IDT 932S421 or 932SQ420 or

equivalent main clock generator. It attenuates jitter on the

input clock and has a selectable PLL bandwidth to

maximize performance in systems with or without

Spread-Spectrum clocking. An SMBus interface allows

control of the PLL bandwidth and bypass options, while 2

clock request (OE#) pins make the 9DB233 suitable for

Express Card applications.

• OE# pins; suitable for Express Card applications

• PLL or bypass mode; PLL can dejitter incoming clock

• Selectable PLL bandwidth; minimizes jitter peaking in

downstream PLL's

• Spread Spectrum Compatible; tracks spreading input

clock for low EMI

• SMBus Interface; allows control of PLL BW and Mode

Key Specifications

• Cycle-to-cycle jitter < 50 ps

• Output-to-output skew < 50 ps

• PCIe Gen3 phase jitter < 1.0ps RMS

Recommended Application

2 output PCIe Gen3 zero-delay/fanout buffer

Output Features

• 2 - 0.7V current mode differential HCSL output pairs

Block Diagram

OE0#

OE1#

DIF_0

DIF_1

SRC_IN

SPREAD

COMPATIBLE

PLL

SRC_IN#

PLL_BW

SMBDAT

SMBCLK

CONTROL

LOGIC

IREF

IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

9DB233

OCTOBER 20, 2016

12 3 4 5 6 7...18

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