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9DB1904BKLF

更新时间： 2024-02-16 22:29:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
18页	172K
描述
19 Output Differential Buffer for PCIe Gen2 and QPI

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9DB1904BKLF 数据手册

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Electrical Characteristics - Absolute Maximum Ratings

PARAMETER

SYMBOL

CONDITIONS

UNITS NOTES

MIN

TYP

MAX

4.6

3.3V Core Supply Voltage

3.3V Logic Supply Voltage

Input Low Voltage

VDDA

VDD

V_IL

1,2

GND-0.5

Input High Voltage

V_IH

Except for SMBus interface

SMBus clock and data pins

V_DD+0.5V

5.5V

^°C

°C

V_IHSMB

Storage Temperature

Junction Temperature

Input ESD protection

ESD prot

-65

150

125

Human Body Model

2000

¹Guaranteed by design and characterization, not 100% tested in production.

²Operation under these conditions is neither implied nor guaranteed.

Electrical Characteristics - Clock Input Parameters

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

600

TYP

800

MAX

1150

UNITS NOTES

Differential inputs

(single-ended measurement)

Differential inputs

Input High Voltage - DIF_IN

V_IHDIF

Input Low Voltage - DIF_IN

V_ILDIF

V_COM

_SS- 300

300

(single-ended measurement)

Input Common Mode

Voltage - DIF_IN

Common Mode Input Voltage

1000

Input Amplitude - DIF_IN

Input Slew Rate - DIF_IN

Input Leakage Current

V_SWING

dv/dt

I_IN

Peak to Peak value

Measured differentially

V_IN= V_{DD ,}V_IN= GND

300

0.4

-5

1450

V/ns

1,2

Input Duty Cycle

d_tin

Measurement from differential wavefrom

Differential Measurement

125

1, 3

Input Jitter - Cycle to Cycle

J_DIFIn

¹Guaranteed by design and characterization, not 100% tested in production.

²Slew rate measured through +/-75mV window centered around differential zero

³Input duty cycle will directly impact output duty cycle in bypass mode. It has no impact in PLL mode.

Electrical Characteristics - Current Consumption

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

I_DD3.3OP

I_DD3.3AOP

I_DD3.3PD

I_DD3.3APD

VDD, All outputs active @100MHz

425

450

Operating Supply Current

VDDA, All outputs active @100MHz

VDD

Powerdown Current

VDDA

Ω

Guaranteed by design and characterization, not 100% tested in production. Zo = 100

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

1 2 3 456 7 8...18

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