Datasheet > 9DB206LLFT

9DB206LLFT

更新时间： 2024-02-22 17:04:25

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	292K
描述
Clock Driver

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9DB206LLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

9DB206LLFT 数据手册

ICS9DB206

Integrated

Circuit

Systems, Inc.

PCI EXPRESS

™

JITTER

ATTENUATOR

GENERAL DESCRIPTION

Features

The ICS9DB206 is a high perfromance 1-to-6 Dif- • Six 0.7V current mode differential HCSL output pairs

ICS

ferential-to-HCSL Jitter Attenuator designed for use

• 1 differential clock input

HiPerClockS™

in PCI Express™ systems. In some PCI Express™

systems, such as those found in desktop PCs, the

PCI Express™ clocks are generated from a low

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

bandwidth, high phase noise PLL frequency synthesizer.In these

systems, a jitter-attenuating device may be necessary in order

to reduce high frequency random and deterministic jitter com-

ponents from the PLL synthesizer and from the system board.

The ICS9DB206 has two PLL bandwidth modes. In low band-

width mode, the PLL loop bandwidth is 500kHz.This setting of-

fers the best jitter attenuation and is still high enough to pass a

triangular input spread spectrum profile. In high bandwidth mode,

the PLL bandwidth is at 1MHz and allows the PLL to pass more

spread spectrum modulation.

• Maximum output frequency: 140MHz

• Output skew: 110ps (maximum)

• Cycle-to-Cycle jitter: 110ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

2.42ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

• Lead-Free package available

For serdes which have x10 reference multipliers instead of x12.5

multipliers, 5 of the 6 PCI Express™ outputs (PCIEX1:5) can be

set for 125MHz instead of 100MHz by configuring the appropri-

ate frequency select pins (FS0:1). Output PCIEX0 will always

run at the reference clock frequency (usually 100MHz) in desk-

top PC PCI Express™ Applications.

BLOCK DIAGRAM

Current

Set

IREF

PIN ASSIGNMENT

1 HiZ

0 Enabled

PLL_BW

CLK

VDDA

GND

IREF

FS1

nOE0

nCLK

FS0

÷5

PCIEXT0

nPCIEXC0

PCIEXT0

PCIEXC0

V^DD

PCIEXT5

PCIEXC5

V^DD

nCLK

CLK

Loop

Filter

GND

PCIEXT1

nPCIEXC1

PCIEXT2

nPCIEXC2

Phase

Detector

0 ÷4

1 ÷5

VCO

PCIEXT1

PCIEXC1

PCIEXT2

PCIEXT4

PCIEXC4

PCIEXT3

PCIEXC2

V^DD

PCIEXC3

V^DD

nOE1

÷5

nOE0

Internal Feedback

FS0

ICS9DB206

28-Lead TSSOP, 173-MIL

4.4mm x 9.7mm x 0.92mm body package

L Package

PCIEXT3

nPCIEXC3

0 ÷5

1 ÷4

PCIEXT4

nPCIEXC4

Top View

PCIEXT5

nPCIEXC5

ICS9DB206

28-Lead, 209-MIL SSOP

5.3mm x 10.2mm x 1.75mm body package

F Package

FS1

1 HiZ

0 Enabled

Top View

nOE1

9DB206CL

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 29, 2004

12 3 4 5 6 7...13

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