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9DB1904BKLF

更新时间： 2024-02-27 21:08:44

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
18页	172K
描述
19 Output Differential Buffer for PCIe Gen2 and QPI

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9DB1904BKLF 数据手册

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Pin Description (continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

Active low input for enabling DIF pair 9.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 10.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 11.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

OE9#

DIF_9

DIF_9#

OUT

OE10#

DIF_10

DIF_10#

OUT

OE11#

DIF_11

DIF_11#

GND

OUT

PWR

0.7V differential Complementary clock output

Ground pin.

Power supply, nominal 3.3V

VDD

Active low input for enabling DIF pair 12.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 13.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 14.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

3.3V Input notifies device to sample latched inputs and start up on first high

assertion, or exit Power Down Mode on subsequent assertions. Low enters

Power Down Mode.

OE12#

DIF_12

DIF_12#

OUT

OE13#

DIF_13

DIF_13#

OUT

OE14#

DIF_14

DIF_14#

OUT

CKPWRGD_PD#

DIF_15

DIF_15#

OUT

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pairs 15 and 16.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Power supply, nominal 3.3V

Ground pin.

0.7V differential true clock output

0.7V differential Complementary clock output

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pairs 17 and 18.

1 =disable outputs, 0 = enable outputs

True Input for differential reference clock.

Complementary Input for differential reference clock.

SMBus address bit 2. When Low, the part operates as a fanout buffer with the

PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with

the PLL operating.

OE15_16#

DIF_ 16

DIF_16#

VDD

OUT

PWR

OUT

GND

DIF_17

DIF_17#

DIF_18

DIF_18#

OE17_18#

CLK_IN

CLK_IN#

SMB_A2_PLLBYP#

0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

1 234 5 6 7...18

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