Datasheet > 9DB106BF

9DB106BF

更新时间： 2023-01-03 07:26:20

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
14页	189K
描述
PLL Based Clock Driver, 9DB Series, 12 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28

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9DB106BF 数据手册

DATASHEET

ICS9DB106

6 Output PCI Express* Buffer with CLKREQ# Function

Description

Features/Benefits

The ICS9DB106 zero-delay buffer supports PCI Express clocking

requirements.The ICS9DB106 is driven by a differential SRC output

pair from an ICS CK409/CK410-compliant main clock generator

such as the ICS952601 or ICS954101. It attenuates jitter on the

input clock and has a selectable PLL bandwidth to maximize

performance in systems with or without Spread-Spectrum clocking.

•

CLKREQ# pin for outputs 1 and 4/output enable for Express

Card applications

PLL or bypass mode/PLL can dejitter incoming clock

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL’s

•

Spread Spectrum Compatible/tracks spreading input clock

for low EMI

SMBus Interface/unused outputs can be disabled

Output Features

Key Specifications

•

6 - 0.7V current mode differential output pairs (HSCL)

SMBus for complete device control

•

Cycle-to-cycle jitter < 35ps

•

Output-to-output skew < 45ps

Funtional Block Diagram

CLKREQ1#

CLKREQ4#

PCIEX1

CLK_INT

SPREAD

COMPATIBLE

PLL

CLK_INC

PCIEX4

PCIEX(0,2,3,5)

PLL_BW

SMBDAT

SMBCLK

CONTROL

LOGIC

IREF

IDT^TM/ICS^TM6 Output PCI Express* Buffer with CLKREQ# Function

ICS9DB106

REV F 12/14/07

12 3 4 5 6 7...14

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