Datasheet > 94215YFLF-T

94215YFLF-T

更新时间： 2024-11-21 06:44:27

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
18页	146K
描述
Processor Specific Clock Generator, 166.66MHz, CMOS, PDSO48

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数据手册

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94215YFLF-T 数据手册

ICS94215

Integrated

Circuit

Systems,Inc.

Programmable System Clock Chip for AMD - K7™ Processor

Recommended Application:

VIA KX/KT133 style chipset

Output Features:

Pin Configuration

VDD1

REF0/CPU_STOP#*

GND

REF1/FS2*

GND

CPUCLK

GND

CPUCLKC0

CPUCLKT0

VDDCPU

PD#*

SDRAM_OUT

GND

SDRAM0

SDRAM1

VDD3

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDD3

SDRAM6

SDRAM7

VDD4

•

1 - Differential pair open drain CPU clocks

1 - CPU clock @ 3.3V

13 - SDRAM @ 3.3V

6 - PCI @3.3V,

1 - 48MHz, @3.3V fixed.

VDD2

*MODE/PCICLK_F

*FS3/PCICLK0

GND

•

1 - 24/48MHz @ 3.3V

2 - REF @3.3V, 14.318MHz.

*SEL24_48#/PCICLK1

PCICLK2

PCICLK3

PCICLK4

VDD2

Features:

•

Programmable ouput frequency.

Programmable ouput rise/fall time.

Programmable PCI_F and PCICLK skew.

Spread spectrum for EMI control typically

by 7dB to 8dB,

BUFFER IN

GND

SDRAM11

SDRAM10

VDD3

SDRAM9

SDRAM8

GND

with programmable spread percentage.

Watchdog timer technology to reset system

if over-clocking causes malfunction.

Uses external 14.318MHz crystal.

FS pins for frequency select

SDATA

SCLK

48MHz/FS0*

24/48MHz/FS1*

•

48-Pin 300mil SSOP

Internal Pull-up Resistor of 120K to VDD

Functionality

Block Diagram

CPU

(MHz)

90.00

PCICLK

(MHz)

30.00

31.67

33.67

34.00

33.57

34.33

35.00

33.33

35.67

36.33

36.67

37.00

37.67

38.33

39.00

33.33

PLL2

FS3

FS2

FS1

FS0

48MHz

24_48MHz

/ 2

95.00

XTAL

OSC

REF (1:0)

CPUCLK

101.00

102.00

100.90

103.00

105.00

100.00

107.00

109.00

110.00

111.00

113.00

115.00

117.00

133.30

PLL1

Spread

Spectrum

CPU

DIVDER

Stop

CPUCLKC0

CPUCLKT0

SEL24_48#

PCI

DIVDER

PCICLK (4:0)

PCICLK_F

Control

Logic

SDATA

SCLK

FS (3:0)

Config.

Reg.

SDRAM

DRIVER

SDRAM (11:0)

SDRAM_OUT

PD#

CPU_STOP#

BUFFER IN

0442C—07/03/02

12 3 4 5 6 7...18

中文翻译

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