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93LC56A/SNRVA PDF预览

93LC56A/SNRVA

更新时间： 2024-02-23 05:41:46
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
12页 222K
描述
EEPROM, 256X8, Serial, CMOS, PDSO8

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93LC56A/SNRVA 技术参数

生命周期：Active包装说明：SOP,
Reach Compliance Code：compliant风险等级：5.59
其他特性：1000000 ERASE/WRITE CYCLES MIN; DATA RETENTION > 200 YEARS最大时钟频率 (fCLK)：2 MHz
数据保留时间-最小值：200JESD-30 代码：R-PDSO-G8
长度：4.9 mm内存密度：2048 bit
内存集成电路类型：EEPROM内存宽度：8
功能数量：1端子数量：8
字数：256 words字数代码：256
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256X8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：SERIAL座面最大高度：1.75 mm
串行总线类型：MICROWIRE最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2.5 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mm最长写入周期时间 (tWC)：6 ms
Base Number Matches：1

93LC56A/SNRVA 数据手册

 浏览型号93LC56A/SNRVA的Datasheet PDF文件第1页浏览型号93LC56A/SNRVA的Datasheet PDF文件第2页浏览型号93LC56A/SNRVA的Datasheet PDF文件第4页浏览型号93LC56A/SNRVA的Datasheet PDF文件第5页浏览型号93LC56A/SNRVA的Datasheet PDF文件第6页浏览型号93LC56A/SNRVA的Datasheet PDF文件第7页 
93LC56A/B  
CLK cycles are not required during the self-timed  
WRITE (i.e., auto ERASE/WRITE) cycle.  
2.0  
PIN DESCRIPTION  
2.1  
Chip Select (CS)  
After detection of a START condition the specified num-  
ber of clock cycles (respectively low to high transitions  
of CLK) must be provided. These clock cycles are  
required to clock in all required opcode, address, and  
data bits before an instruction is executed (Table 2-1  
and Table 2-2). CLK and DI then become don't care  
inputs waiting for a new START condition to be  
detected.  
A high level selects the device; a low level deselects the  
device and forces it into standby mode. However, a pro-  
gramming cycle which is already in progress will be  
completed, regardless of the Chip Select (CS) input  
signal. If CS is brought low during a program cycle, the  
device will go into standby mode as soon as the pro-  
gramming cycle is completed.  
2.3  
Data In (DI)  
CS must be low for 250 ns minimum (TCSL) between  
consecutive instructions. If CS is low, the internal con-  
trol logic is held in a RESET status.  
Data In is used to clock in a START bit, opcode,  
address, and data synchronously with the CLK input.  
2.2  
Serial Clock (CLK)  
2.4  
Data Out (DO)  
The Serial Clock is used to synchronize the communi-  
cation between a master device and the 93LC56A/B.  
Opcode, address, and data bits are clocked in on the  
positive edge of CLK. Data bits are also clocked out on  
the positive edge of CLK.  
Data Out is used in the READ mode to output data syn-  
chronously with the CLK input (TPD after the positive  
edge of CLK).  
This pin also provides READY/BUSY status information  
during ERASE and WRITE cycles. READY/BUSY sta-  
tus information is available on the DO pin if CS is  
brought high after being low for minimum chip select  
low time (TCSL) and an ERASE or WRITE operation  
has been initiated.  
CLK can be stopped anywhere in the transmission  
sequence (at high or low level) and can be continued  
anytime with respect to clock high time (TCKH) and  
clock low time (TCKL). This gives the controlling master  
freedom in preparing opcode, address, and data.  
The status signal is not available on DO, if CS is held  
low during the entire ERASE or WRITE cycle. In this  
case, DO is in the HIGH-Z mode. If status is checked  
after the ERASE/WRITE cycle, the data line will be high  
to indicate the device is ready.  
CLK is a “Don't Care” if CS is low (device deselected).  
If CS is high, but START condition has not been  
detected, any number of clock cycles can be received  
by the device without changing its status (i.e., waiting  
for START condition).  
TABLE 2-1  
INSTRUCTION SET FOR 93LC56A  
Instruction SB Opcode  
Address  
Data In  
Data Out  
Req. CLK Cycles  
1
1
1
1
1
1
1
11  
00  
00  
00  
10  
01  
00  
X
1
0
1
X
X
0
A7 A6 A5 A4 A3 A2 A1 A0  
—
—
—
—
—
(RDY/BSY)  
(RDY/BSY)  
HIGH-Z  
12  
12  
12  
12  
20  
20  
20  
ERASE  
ERAL  
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EWDS  
EWEN  
READ  
WRITE  
WRAL  
HIGH-Z  
A7 A6 A5 A4 A3 A2 A1 A0  
D7 - D0  
A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0  
(RDY/BSY)  
(RDY/BSY)  
1
X
X
X
X
X
X
X
D7 - D0  
TABLE 2-2  
INSTRUCTION SET FOR 93LC56B  
Address  
Instruction SB Opcode  
Data In  
Data Out  
Req. CLK Cycles  
1
1
1
1
1
1
1
11  
00  
00  
00  
10  
01  
00  
X
1
0
1
X
X
0
A6 A5 A4 A3 A2 A1 A0  
—
—
—
—
—
(RDY/BSY)  
(RDY/BSY)  
HIGH-Z  
11  
11  
11  
11  
27  
27  
27  
ERASE  
ERAL  
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EWDS  
EWEN  
READ  
WRITE  
WRAL  
HIGH-Z  
A6 A5 A4 A3 A2 A1 A0  
D15 - D0  
A6 A5 A4 A3 A2 A1 A0 D15 - D0  
D15 - D0  
(RDY/BSY)  
(RDY/BSY)  
1
X
X
X
X
X
X
1998 Microchip Technology Inc.  
DS21208C-page 3  
1234567...12

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