Datasheet > 存储 > EEPROM> 93LC56A-I/P

93LC56A-I/P

更新时间： 2024-02-27 16:38:00

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路微波光电二极管 PC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
12页	163K
描述
2K 2.5V Microwave Serial EEPROM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

93LC56A-I/P 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	SOIC
包装说明：	0.150 INCH, PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	compliant	风险等级：	5.17
Is Samacsys：	N	其他特性：	100K ERASE/WRITE CYCLES MIN; DATA RETENTION > 40 YEARS
备用内存宽度：	8	最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	200	耐久性：	10000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	内存密度：	2048 bit
内存集成电路类型：	EEPROM	内存宽度：	16
湿度敏感等级：	1	功能数量：	1
端子数量：	8	字数：	128 words
字数代码：	128	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128X16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	3/5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
串行总线类型：	MICROWIRE	最大待机电流：	0.00003 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3.9 mm
最长写入周期时间 (tWC)：	10 ms	写保护：	SOFTWARE
Base Number Matches：	1

93LC56A-I/P 数据手册

93LC56A/B

CLK cycles are not required during the self-timed

WRITE (i.e., auto ERASE/WRITE) cycle.

2.0

PIN DESCRIPTION

2.1

Chip Select (CS)

After detection of a START condition the speciﬁed num-

ber of clock cycles (respectively low to high transitions

of CLK) must be provided. These clock cycles are

required to clock in all required opcode, address, and

data bits before an instruction is executed (Table 2-1

and Table 2-2). CLK and DI then become don't care

inputs waiting for a new START condition to be

detected.

A high level selects the device; a low level deselects the

device and forces it into standby mode. However, a pro-

gramming cycle which is already in progress will be

completed, regardless of the Chip Select (CS) input

signal. If CS is brought low during a program cycle, the

device will go into standby mode as soon as the pro-

gramming cycle is completed.

2.3

Data In (DI)

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal con-

trol logic is held in a RESET status.

Data In is used to clock in a START bit, opcode,

address, and data synchronously with the CLK input.

2.2

Serial Clock (CLK)

2.4

Data Out (DO)

The Serial Clock is used to synchronize the communi-

cation between a master device and the 93LC56A/B.

Opcode, address, and data bits are clocked in on the

positive edge of CLK. Data bits are also clocked out on

the positive edge of CLK.

Data Out is used in the READ mode to output data syn-

chronously with the CLK input (TPD after the positive

edge of CLK).

This pin also provides READY/BUSY status information

during ERASE and WRITE cycles. READY/BUSY sta-

tus information is available on the DO pin if CS is

brought high after being low for minimum chip select

low time (TCSL) and an ERASE or WRITE operation has

been initiated.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (TCKH) and

clock low time (TCKL). This gives the controlling master

freedom in preparing opcode, address, and data.

The status signal is not available on DO, if CS is held

low during the entire ERASE or WRITE cycle. In this

case, DO is in the HIGH-Z mode. If status is checked

after the ERASE/WRITE cycle, the data line will be high

to indicate the device is ready.

CLK is a “Don't Care” if CS is low (device deselected).

If CS is high, but START condition has not been

detected, any number of clock cycles can be received

by the device without changing its status (i.e., waiting

for START condition).

TABLE 2-1

INSTRUCTION SET FOR 93LC56A

Instruction SB Opcode

Address

Data In

Data Out

Req. CLK Cycles

A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

HIGH-Z

ERASE

ERAL

EWDS

EWEN

READ

WRITE

WRAL

HIGH-Z

A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0

(RDY/BSY)

D7 - D0

TABLE 2-2

INSTRUCTION SET FOR 93LC56B

Instruction SB Opcode

Address

Data In

Data Out

Req. CLK Cycles

A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

HIGH-Z

ERASE

ERAL

EWDS

EWEN

READ

WRITE

WRAL

HIGH-Z

A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

A6 A5 A4 A3 A2 A1 A0 D15 - D0

D15 - D0

1997 Microchip Technology Inc.

Preliminary

DS21208A-page 3

1 234 5 6 7...12

下载PDF

与93LC56A-I/P相关器件

型号	品牌	描述	获取价格	数据表
93LC56AI/PG	MICROCHIP	2K Microwire Compatible Serial EEPROM	获取价格
93LC56A-I/SM	MICROCHIP	2K 2.5V Microwave Serial EEPROM	获取价格
93LC56AI/SN	MICROCHIP	2K Microwire Compatible Serial EEPROM	获取价格
93LC56A-I/SN	MICROCHIP	2K 2.5V Microwave Serial EEPROM	获取价格
93LC56A-I/SNA22	MICROCHIP	256 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8	获取价格
93LC56AI/SNG	MICROCHIP	2K Microwire Compatible Serial EEPROM	获取价格

与93LC56A-I/P相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

13
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

93LC56A-I/P

93LC56A-I/P 技术参数

93LC56A-I/P 数据手册

与93LC56A-I/P相关器件

与93LC56A-I/P相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

93LC56A-I/P

93LC56A-I/P 技术参数

93LC56A-I/P 数据手册

与93LC56A-I/P相关器件

与93LC56A-I/P相关文章

您还可以找

您在本页遇到什么问题？