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93LC46XT

更新时间： 2024-02-19 01:52:30
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
20页 321K
描述
1K/2K/4K 2.5V Microwire Serial EEPROM

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93LC46XT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51Factory Lead Time：9 weeks
风险等级：5.24Is Samacsys：N
其他特性：3 WIRE INTERFACE; AUTOMATIC WRITE; ERAL AT 4.5V TO 6.0V备用内存宽度：8
最大时钟频率 (fCLK)：2 MHz数据保留时间-最小值：200
耐久性：1000000 Write/Erase CyclesJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
内存密度：1024 bit内存集成电路类型：EEPROM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：8
字数：64 words字数代码：64
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64X16
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.75 mm
串行总线类型：MICROWIRE最大待机电流：0.00003 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.9 mm
最长写入周期时间 (tWC)：10 ms写保护：SOFTWARE
Base Number Matches：1

93LC46XT 数据手册

 浏览型号93LC46XT的Datasheet PDF文件第7页浏览型号93LC46XT的Datasheet PDF文件第8页浏览型号93LC46XT的Datasheet PDF文件第9页浏览型号93LC46XT的Datasheet PDF文件第11页浏览型号93LC46XT的Datasheet PDF文件第12页浏览型号93LC46XT的Datasheet PDF文件第13页 
93LC46/56/66  
3.0  
PIN DESCRIPTION  
The descriptions of the pins are listed in Table 3-1.  
TABLE 3-1:  
Name  
PIN FUNCTION TABLE  
PDIP  
ROTATED  
TSSOP  
SOIC  
Description  
CS  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
3
4
5
6
7
8
1
2
Chip Select  
CLK  
DI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
DO  
VSS  
ORG  
NU  
Memory Configuration  
Not Utilized  
Vcc  
+1.8V to 5.5V Power Supply  
3.1  
Chip Select (CS)  
Note:  
CS must go low between consecutive  
instructions.  
A high level selects the device. A low level deselects  
the device and forces it into Standby mode. However, a  
programming cycle which is already initiated and/or in  
progress will be completed, regardless of the CS input  
signal. If CS is brought low during a program cycle, the  
device will go into Standby mode as soon as the  
programming cycle is completed.  
3.3  
Data In (DI)  
Data In is used to clock in a Start bit, opcode, address  
and data synchronously with the CLK input.  
3.4  
Data Out (DO)  
CS must be low for 250 ns minimum (TCSL) between  
consecutive instructions. If CS is low, the internal  
control logic is held in a Reset status.  
Data Out is used in the Read mode to output data syn-  
chronously with the CLK input (TPD after the positive  
edge of CLK).  
3.2  
Serial Clock (CLK)  
This pin also provides Ready/Busy status information  
during erase and write cycles. Ready/Busy status infor-  
mation is available on the DO pin if CS is brought high  
after being low for minimum chip select low time (TCSL)  
and an erase or write operation has been initiated.  
The serial clock is used to synchronize the communica-  
tion between a master device and the 93LC46/56/66.  
Opcode, address and data bits are clocked in on the  
positive edge of CLK. Data bits are also clocked out on  
the positive edge of CLK.  
The Status signal is not available on DO, if CS is held  
low or high during the entire write or erase cycle. In all  
other cases DO is in the High-Z mode. If status is  
checked after the write/erase cycle, a pull-up resistor  
on DO is required to read the Ready signal.  
CLK can be stopped anywhere in the transmission  
sequence (at high or low level) and can be continued  
anytime with respect to clock high time (TCKH) and  
clock low time (TCKL). This gives the controlling master  
freedom in preparing opcode, address and data.  
3.5  
Organization (ORG)  
CLK is a “don't care” if CS is low (device deselected). If  
CS is high, but Start condition has not been detected,  
any number of clock cycles can be received by the  
device without changing its status (i.e., waiting for Start  
condition).  
When ORG is connected to VCC, the (x16) memory  
organization is selected. When ORG is tied to VSS, the  
(x8) memory organization is selected. ORG can only be  
floated for clock speeds of 1 MHz or less for the (x16)  
memory organization. For clock speeds greater than  
1 MHz, ORG must be tied to VCC or VSS.  
CLK cycles are not required during the self-timed write  
(i.e., auto erase/write) cycle.  
After detection of a Start condition the specified number  
of clock cycles (respectively low-to-high transitions of  
CLK) must be provided. These clock cycles are required  
to clock in all required opcode, address and data bits  
before an instruction is executed (see instruction set  
truth table). CLK and DI then become “don't care” inputs  
waiting for a new Start condition to be detected.  
DS21712C-page 10  
2002-2012 Microchip Technology Inc.  
1...78910111213...20

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