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93LC46XT

更新时间： 2024-01-01 04:36:42
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
20页 321K
描述
1K/2K/4K 2.5V Microwire Serial EEPROM

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93LC46XT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51Factory Lead Time：9 weeks
风险等级：5.24Is Samacsys：N
其他特性：3 WIRE INTERFACE; AUTOMATIC WRITE; ERAL AT 4.5V TO 6.0V备用内存宽度：8
最大时钟频率 (fCLK)：2 MHz数据保留时间-最小值：200
耐久性：1000000 Write/Erase CyclesJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
内存密度：1024 bit内存集成电路类型：EEPROM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：8
字数：64 words字数代码：64
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64X16
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.75 mm
串行总线类型：MICROWIRE最大待机电流：0.00003 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.9 mm
最长写入周期时间 (tWC)：10 ms写保护：SOFTWARE
Base Number Matches：1

93LC46XT 数据手册

 浏览型号93LC46XT的Datasheet PDF文件第4页浏览型号93LC46XT的Datasheet PDF文件第5页浏览型号93LC46XT的Datasheet PDF文件第6页浏览型号93LC46XT的Datasheet PDF文件第8页浏览型号93LC46XT的Datasheet PDF文件第9页浏览型号93LC46XT的Datasheet PDF文件第10页 
93LC46/56/66  
The DO pin indicates the Ready/Busy status of the  
device if CS is brought high after a minimum of 250 ns  
low (TCSL) and before the entire write cycle is complete.  
2.7  
Write  
The WRITE instruction is followed by 16 bits (or by 8  
bits) of data which are written into the specified  
address. After the last data bit is put on the DI pin,  
CS must be brought low before the next rising edge  
of the CLK clock. This falling edge of CS initiates the  
self-timed auto-erase and programming cycle.  
The ERAL cycle takes (8 ms typical).  
2.9  
Write All (WRAL)  
The WRAL instruction will write the entire memory array  
with the data specified in the command. The WRAL  
cycle is completely self-timed and commences at the  
falling edge of the CS. Clocking of the CLK pin is not  
necessary after the device has entered the self clock-  
ing mode. The WRAL command does include an auto-  
matic ERAL cycle for the device. Therefore, the WRAL  
instruction does not require an ERAL instruction but the  
chip must be in the EWEN status. The WRAL instruction  
is ensured at 5V ±10%.  
The DO pin indicates the Ready/Busy status of the  
device if CS is brought high after a minimum of 250 ns  
low (TCSL) and before the entire write cycle is complete.  
DO at logical “0” indicates that programming is still in  
progress. DO at logical “1” indicates that the register at  
the specified address has been written with the data  
specified and the device is ready for another  
instruction.  
The write cycle takes 4 ms per word typical.  
The DO pin indicates the Ready/Busy status of the  
device if CS is brought high after a minimum of 250 ns  
low (Tcsl).  
2.8  
Erase All (ERAL)  
The ERAL instruction will erase the entire memory array  
to the logical “1” state. The ERAL cycle is identical to  
the ERASE cycle except for the different opcode. The  
ERAL cycle is completely self-timed and commences  
at the falling edge of the CS. Clocking of the CLK pin is  
not necessary after the device has entered the self  
clocking mode. The ERAL instruction is ensured at 5V  
±10%.  
The WRAL cycle takes 16 ms typical.  
FIGURE 2-1:  
READ TIMING  
CS  
CLK  
DI  
A0  
An •••  
1
1
0
High-Z  
DO  
0
Dx ••• D0 Dx  
••• D0 Dx  
••• D0  
2002-2012 Microchip Technology Inc.  
DS21712C-page 7  
1...45678910...20

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